Abstract: A method of fabricating a small bipolar transistor emitter in an integrated circuit structure is provided. The integrated circuit structure includes a trench isolation structure formed in a semiconductor substrate to define a substrate active device region. A collector region having a first conductivity type is formed in the substrate active device region beneath a surface thereof. A base region having a second conductivity type opposite the first conductivity type is formed in the substrate active device region above the collector region and extending to the surface of the substrate active device region such that the surface of the active device region forms a surface of the base region. A layer of dielectric material is formed to extend at least partially over the surface of the base region to define an edge of the layer of dielectric material that is formed over the surface of the base region.

Abstract: A method of simultaneously forming refractory metal salicide and a local interconnect proceeds, after the standard formation of N+ and P+ junctions, by depositing titanium and TiN films and annealing the structure in nitrogen ambient to form a salicide film on the exposed source, drain and gate regions. A local interconnect mask is then employed to form local interconnect resist patterns. The TiN and unreacted titanium film are then etched off using a wet strip without attacking either salicide or field oxide. Following the etch, the salicide and local interconnect are again subjected to a rapid thermal anneal in a nitrogen ambient to reduce the sheet resistance of the salicide and the local interconnect and to convert the remaining titanium in the local interconnect into TiN film. The process flow can also be applied if cobalt is used instead of titanium and the cobalt is covered with a TiN cap.

Abstract: A MOS transistor structure is provided in which the source/drain contacts are to raised polysilicon and are located entirely over field isolation. Contact integrity is maintained because the contact is located on field oxide, rather than in direct contact with the substrate junction diffusion area. Conventional contact metal spiking into the junction area is also eliminated. Contact overetch during formation of the contact opening can be increased to insure a clean contact surface because the contact is made to the raised poly regions. Furthermore, the contact barrier is no longer essential for maintaining contact reliability, because the contact is located away from the active junction.

Abstract: A method of fabricating a MOSFET device structure, wherein the MOSFET device structure includes field oxide regions, a layer of gate oxide formed on the substrate, oxide sidewall spacers formed on sidewalls of the polysilicon gate, and LDD N- regions formed in the substrate adjacent the field oxide regions and beneath the sidewall spacers. A second layer of polysilicon is deposited over the above-described structure and a chemical mechanical polishing step is performed to self-align the polysilicon source/drain regions to the LDD N- substrate regions. N+ type dopant is then implanted into the gate poly and into the raised source/drain polysilicon regions. Next, a rapid thermal anneal step is performed to activate the N+ implant and to outdiffuse the N+ dopant from the polysilicon raised source/drain regions to form an N+ junction inside the N- LDD source/drain regions.

Abstract: MOSFET device structure includes planarized trench isolation field oxide regions formed in a silicon substrate, a layer of gate oxide formed on the substrate to electrically insulate the polysilicon gate from the substrate, oxide sidewall spacers formed on sidewalls of the polysilicon gate and the gate oxide, and LDD N-regions formed in the substrate adjacent to the field oxide regions and beneath the sidewall spacers to define a channel region in the substrate beneath the polysilicon gate. A layer of polysilicon is deposited on the above-defined structure and a chemical mechanical polishing step is performed to form raised source/drain polysilicon regions that are self-aligned to the LDD N- regions. N-type dopant is then implanted into the polysilicon gate and into the raised source/drain polysilicon regions.

Abstract: A MOSFET design is provided that utilizes raised poly source/drain regions in a novel manner, thereby reducing the problems associated with conventional MOSFET designs, including the "short channel effect." The "short channel effect" is reduced by forming the N+ junction inside the N- LDD diffusion by outdiffusing from the overlying doped poly. Junctions are formed from doped poly using a POCl.sub.3 source self-aligned to the gate, source and drain regions, and RTA to drive dopant from the poly into the silicon substrate. Since the raised poly source/drain regions extend over field oxide, the source/drain junction areas are much smaller; parasitic capacitances are greatly reduced and device speed is enhanced. The process results in low resistivity compared to conventional techniques, even without the use of salicide. Since there is no gate implantation, there is a reduced risk of damage to the gate oxide.