Patents by Inventor Abdelaziz Goulahsen
Abdelaziz Goulahsen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10558587Abstract: A method for reading or writing data at an address of a memory is disclosed. The data includes a number of consecutive words that each has a plurality of bits. The words are transferred to or from the memory in synchronization with a clock signal so that each word is transferred in one cycle of the clock signal. The bits are scrambled or unscrambled by applying a logic function to the bits of each word. The logic function is identical for the scrambling and the unscrambling and makes use of a bit-key that is dedicated to the word and is identical for the scrambling and the unscrambling. Each bit-key comes from a pseudo-random series generated based on the address.Type: GrantFiled: February 28, 2017Date of Patent: February 11, 2020Assignees: STMICROELECTRONICS (GRAND OUEST) SAS, STMICROELECTRONICS (GRENOBLE 2) SASInventors: Abdelaziz Goulahsen, Patrice Derouet
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Patent number: 10114687Abstract: A method of verifying integrity of communications between a master circuit and a slave circuit includes updating a first cyclic multibit signature based on each transaction sent by the master circuit to the slave circuit. A second cyclic multibit signature is updated based on each transaction received by the slave circuit. One or more bits based on the second cyclic multibit signature are compared with corresponding bits based on the first cyclic multibit signature, with a number of the one or more bits being less than a total number of bits of the second cyclic signature. Error conditions are detected and responded based on the comparing.Type: GrantFiled: November 23, 2015Date of Patent: October 30, 2018Assignee: STMICROELECTRONICS (GRENOBLE 2) SASInventors: Gilles Ries, Abdelaziz Goulahsen
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Patent number: 10056923Abstract: The invention relates to a method for serial data transmission, comprising the steps consisting in computing the running disparity (RD) of a bit stream that is being transmitted; when the running disparity reaches a threshold (T), computing a point disparity on a subsequent frame (S) of the stream; if the point disparity has the same sign as the threshold, inverting the states of the bits of the frame in the transmitted bit stream; and inserting into the transmitted bit stream a polarity bit having a state signalling the inversion.Type: GrantFiled: September 1, 2017Date of Patent: August 21, 2018Assignees: STMICROELECTRONICS (GRENOBLE 2) SAS, STMICROELECTRONICS (ALPS) SASInventors: Julien Saade, Abdelaziz Goulahsen
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Publication number: 20180067872Abstract: A method for reading or writing data at an address of a memory is disclosed. The data includes a number of consecutive words that each has a plurality of bits. The words are transferred to or from the memory in synchronization with a clock signal so that each word is transferred in one cycle of the clock signal. The bits are scrambled or unscrambled by applying a logic function to the bits of each word. The logic function is identical for the scrambling and the unscrambling and makes use of a bit-key that is dedicated to the word and is identical for the scrambling and the unscrambling. Each bit-key comes from a pseudo-random series generated based on the address.Type: ApplicationFiled: February 28, 2017Publication date: March 8, 2018Inventors: Abdelaziz Goulahsen, Patrice Derouet
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Publication number: 20170366207Abstract: The invention relates to a method for serial data transmission, comprising the steps consisting in computing the running disparity (RD) of a bit stream that is being transmitted; when the running disparity reaches a threshold (T), computing a point disparity on a subsequent frame (S) of the stream; if the point disparity has the same sign as the threshold, inverting the states of the bits of the frame in the transmitted bit stream; and inserting into the transmitted bit stream a polarity bit having a state signalling the inversion.Type: ApplicationFiled: September 1, 2017Publication date: December 21, 2017Inventors: Julien SAADE, Abdelaziz Goulahsen
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Patent number: 9847798Abstract: The invention relates to a method for serial data transmission, comprising the steps consisting in computing the running disparity (RD) of a bit stream that is being transmitted; when the running disparity reaches a threshold (T), computing a point disparity on a subsequent frame (S) of the stream; if the point disparity has the same sign as the threshold, inverting the states of the bits of the frame in the transmitted bit stream; and inserting into the transmitted bit stream a polarity bit having a state signalling the inversion.Type: GrantFiled: December 8, 2015Date of Patent: December 19, 2017Assignees: STMICROELECTRONICS (GRENOBLE 2) SAS, STMICROELECTRONICS (ALPS) SASInventors: Julien Saade, Abdelaziz Goulahsen
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Patent number: 9831979Abstract: A device for transmitting a signal over a serial link includes a transmission processor to carry out, before transmission over the serial link, a scrambling process on successive initial packets of the signal to form a scrambled packet for each initial packet. The transmission processor includes an encoding circuit to carry out an encoding process on each initial packet to deliver an encoded packet. The encoding process includes, for each current initial packet starting from the second, encoding of the current initial packet with the preceding scrambled packet. Calculation circuitry determines, for each initial packet, a bit disparity of the encoded packet and determination of a cumulative bit disparity. Comparison circuitry carries out a comparison process involving the bit disparity of the encoded packet and the cumulative disparity, with the scrambled packet being the encoded packet or the inverted encoded packet, depending on the result of the comparison process.Type: GrantFiled: August 26, 2015Date of Patent: November 28, 2017Assignee: STMICROELECTRONICS (GRENOBLE 2) SASInventor: Abdelaziz Goulahsen
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Patent number: 9767056Abstract: Transaction exchanges are controlled between two integrated circuits in a system having the integrated circuits (ICs), a power supply supplying power to a link between the ICs, thereby enabling transaction exchanges between both ICs and a controller controlling the ICs and the power supply. This involves receiving an order at the controller, wherein the order requires the link to be closed. An instruction is sent from the controller to each of the two ICs, wherein the instruction causes each of the ICs to stop initiating new transaction requests. For each one of the ICs, in response to detecting that the one of the two ICs has stopped initiating new transactions, it is detected when all pending transactions initiated by the one of the two ICs have been executed. The link is closed in response to detecting that all pending transactions of both of the two ICs have been executed.Type: GrantFiled: July 6, 2012Date of Patent: September 19, 2017Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (publ)Inventors: Bipin Balakrishnan, Abdelaziz Goulahsen
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Patent number: 9762383Abstract: A method for transmitting data in series includes producing a scrambled signal by applying a scrambling using a pseudo-random sequence to an incoming serial signal conveying the data and producing an outgoing serial signal. The scrambled signal is monitored to detect occurrences of one or more data patterns. In response to the detection of one or more occurrences, one or more actions are taken to protect data in the output signal.Type: GrantFiled: May 20, 2016Date of Patent: September 12, 2017Assignees: STMICROELECTRONICS (GRENOBLE 2) SAS, STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Julien Saade, Abdelaziz Goulahsen
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Patent number: 9647826Abstract: A system may include a first device, a second device, a third device, and a serial link between the second device and the third device. The first device may be configured to deliver to the second device an information stream having a transmission fault tolerance associated with a transmission by the second device to the third device over the serial link. A related method may include, during the transmission over the serial link, phases for synchronization between the second and third devices, and during each synchronization phase, the first device may continue to deliver the information stream to the second device.Type: GrantFiled: April 17, 2015Date of Patent: May 9, 2017Assignee: STMICROELECTRONICS (GRENOBLE 2) SASInventors: Abdelaziz Goulahsen, Gilles Ries
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Publication number: 20160378580Abstract: A method of verifying integrity of communications between a master circuit and a slave circuit includes updating a first cyclic multibit signature based on each transaction sent by the master circuit to the slave circuit. A second cyclic multibit signature is updated based on each transaction received by the slave circuit. One or more bits based on the second cyclic multibit signature are compared with corresponding bits based on the first cyclic multibit signature, with a number of the one or more bits being less than a total number of bits of the second cyclic signature. Error conditions are detected and responded based on the comparing.Type: ApplicationFiled: November 23, 2015Publication date: December 29, 2016Inventors: Gilles Ries, Abdelaziz Goulahsen
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Publication number: 20160269173Abstract: A method for transmitting data in series includes producing a scrambled signal by applying a scrambling using a pseudo-random sequence to an incoming serial signal conveying the data and producing an outgoing serial signal. The scrambled signal is monitored to detect occurrences of one or more data patterns. In response to the detection of one or more occurrences, one or more actions are taken to protect data in the output signal.Type: ApplicationFiled: May 20, 2016Publication date: September 15, 2016Inventors: Julien SAADE, Abdelaziz GOULAHSEN
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Patent number: 9442552Abstract: It is proposed a method for regulating the activity of a core running at a given clock rate. The method comprises: monitoring (S100) a value of a parameter of the core, the parameter being a critical parameter for a safe operating of the core; determining whether the monitored value reaches a trigger value; when the monitored value reaches the trigger value (S120): modifying the clock rate of the core (S130) by decreasing the ratio of active cycles of the clock; and running the core at the clock rate modified (S140) by decreasing the ratio of active cycles of the clock; when the monitored value reaches a second time the trigger value (S170): modifying the clock rate of the core (S180) by increasing the ratio of active cycles of the clock; and running the core at the clock rate (S190) modified by increasing the ratio of active cycles of the clock.Type: GrantFiled: September 6, 2012Date of Patent: September 13, 2016Assignee: ST-Ericsson SAInventors: Gilles Ries, Abdelaziz Goulahsen
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Publication number: 20160233896Abstract: The invention relates to a method for serial data transmission, comprising the steps consisting in computing the running disparity (RD) of a bit stream that is being transmitted; when the running disparity reaches a threshold (T), computing a point disparity on a subsequent frame (S) of the stream; if the point disparity has the same sign as the threshold, inverting the states of the bits of the frame in the transmitted bit stream; and inserting into the transmitted bit stream a polarity bit having a state signalling the inversion.Type: ApplicationFiled: December 8, 2015Publication date: August 11, 2016Inventors: Julien SAADE, Abdelaziz GOULAHSEN
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Patent number: 9391769Abstract: A method for transmitting data in series includes producing a scrambled signal by applying a scrambling using a pseudo-random sequence to an incoming serial signal conveying the data and producing an outgoing serial signal from the scrambled signal. After each sequence of N consecutive bits at the same state in the scrambled signal, a dummy bit of reverse state is inserted in the outgoing signal.Type: GrantFiled: October 8, 2014Date of Patent: July 12, 2016Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics International N.V.Inventors: Julien Saade, Abdelaziz Goulahsen
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Publication number: 20160072610Abstract: A device for transmitting a signal over a serial link includes a transmission processor to carry out, before transmission over the serial link, a scrambling process on successive initial packets of the signal to form a scrambled packet for each initial packet. The transmission processor includes an encoding circuit to carry out an encoding process on each initial packet to deliver an encoded packet. The encoding process includes, for each current initial packet starting from the second, encoding of the current initial packet with the preceding scrambled packet. Calculation circuitry determines, for each initial packet, a bit disparity of the encoded packet and determination of a cumulative bit disparity. Comparison circuitry carries out a comparison process involving the bit disparity of the encoded packet and the cumulative disparity, with the scrambled packet being the encoded packet or the inverted encoded packet, depending on the result of the comparison process.Type: ApplicationFiled: August 26, 2015Publication date: March 10, 2016Inventor: Abdelaziz GOULAHSEN
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Publication number: 20150312006Abstract: A system may include a first device, a second device, a third device, and a serial link between the second device and the third device. The first device may be configured to deliver to the second device an information stream having a transmission fault tolerance associated with a transmission by the second device to the third device over the serial link. A related method may include, during the transmission over the serial link, phases for synchronization between the second and third devices, and during each synchronization phase, the first device may continue to deliver the information stream to the second device.Type: ApplicationFiled: April 17, 2015Publication date: October 29, 2015Inventors: Abdelaziz GOULAHSEN, Gilles RIES
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Patent number: 9154294Abstract: This invention concerns a resynchronization method by a receiver of a received stream of groups of bits, comprising: detecting a synchronization loss (S10), and then iterating (S11 to S17) checks over different bits until a first bit of a group of bits is found (S14), the most probable first bit being checked first, wherein the checks are iterated in a checking order of bits different from a chronological reception order, so as to check earlier at least one of most probable first bits, different from the most probable first bit, so as to shorten average resynchronization time.Type: GrantFiled: February 1, 2013Date of Patent: October 6, 2015Assignee: ST-ERICSSON SAInventors: Gilles Ries, Abdelaziz Goulahsen
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Publication number: 20150139420Abstract: A method for transmitting data in series includes producing a scrambled signal by applying a scrambling using a pseudo-random sequence to an incoming serial signal conveying the data and producing an outgoing serial signal from the scrambled signal. After each sequence of N consecutive bits at the same state in the scrambled signal, a dummy bit of reverse state is inserted in the outgoing signal.Type: ApplicationFiled: October 8, 2014Publication date: May 21, 2015Inventors: Julien Saade, Abdelaziz Goulahsen
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Publication number: 20140369447Abstract: This invention concerns a resynchronization method by a receiver of a received stream of groups of bits, comprising: detecting a synchronization loss (S10), and then iterating (S11 to S17) checks over different bits until a first bit of a group of bits is found (S14), the most probable first bit being checked first, wherein the checks are iterated in a checking order of bits different from a chronological reception order, so as to check earlier at least one of most probable first bits, different from the most probable first bit, so as to shorten average resynchronization time.Type: ApplicationFiled: February 1, 2013Publication date: December 18, 2014Inventors: Gilles Ries, Abdelaziz Goulahsen