Abstract: Systems and methods for digital-based, standards-compatible, testing of analog circuits embedded inside integrated circuits. In this regard, one such system can be broadly described by a test stimulus generator that transmits a binary-level test-stimulus signal into an analog circuit located inside an integrated circuit; a converter that converts an analog output signal from the analog circuit into a digital output signal; a boundary-scan register chain that transmits the digital output signal out of the integrated circuit, and a test equipment that receives the digital output signal using the IEEE 1149.1 boundary-scan standard and analyzes the digital output signal to compute one or more specifications of the analog circuit located inside the integrated circuit.

Abstract: A low cost signature test for RF and analog circuits. A model is provided to predict one or more performance parameters characterizing a first electronic circuit produced by a manufacturing process subject to process variation from the output of one or more second electronic circuits produced by the same process in response to a selected test stimulus, and iteratively varying the test stimulus to minimize the error between the predicted performance parameters and corresponding measured values for the performance parameters, for determining an optimized test stimulus. A non-linear model is preferably constructed for relating signature test results employing the optimized test stimulus in manufacturing testing to circuit performance parameters.

Abstract: The present invention relates to two novel Gonadotropin releasing hormones muGnRH I and muGnRH II of amino acid SEQ ID 1 as QHWSAWRLPG, and SEQ ID 2 QHWSWGILPG respectively, useful for induced breeding in fish both in combination and alone, by activating production of Gonadotropin, and a method of isolating the same from Indian Murrel brain, and further, a method of inducing breeding in fishes using the said novel gonadotropin releasing hormones.

Abstract: A method for testing a system on a chip or a system on a package (““SOPC”) having a plurality of internal modules that are tested to determine whether predetermined performance specifications are satisfied. A first module of the SOPC is selected for testing. A determination is made as to whether the first module is directly accessible or not. If the first module is directly accessible, the module may be tested with automated test equipment external to the SOPC. If the first module is not directly accessible, the module may be tested with a second and third module of the SOPC.

Abstract: The present invention relates to two novel Gonadotropin releasing hormones muGnRH I and muGnRH II of amino acid SEQ ID 1 as QHWSAWRLPG, and SEQ ID 2 QHWSWGILPG respectively, useful for induced breeding in fish both in combination and alone, by activating production of Gonadotropin, and a method of isolating the same from Indian Murrel brain, and further, a method of inducing breeding in fishes using the said novel gonadotropin releasing hormones.

Abstract: A method for using an alternate performance test to reduce test time and improve manufacturing yield. The method comprises establishing a specification test limit within which a product would be accepted under specification test criteria and inner and outer alternate test error bounds relative to the specification test limit; initially testing the product with the alternate test; accepting the product if the alternate test result is within the inner alternate test error bound; rejecting the product if the alternate test result is outside the outer alternate test error bound; and retesting the product using the specification test if the alternate test result is on or between the alternate error bounds. On retesting, the product is ordinarily rejected if the specification test result is outside the specification test limits. The method may further comprise modifying a production test to produce a specification test whose guardband is narrower than the production test.

Abstract: The present invention relates to two novel Gonadotropin releasing hormones muGnRH I and muGnRH II of amino acid SEQ ID 1 as QHWSAWRLPG, and SEQ ID 2 QHWSWGILPG respectively, useful for induced breeding in fish both in combination and alone, by activating production of Gonadotropin, and a method of isolating the same from Indian Murrel brain, and further, a method of inducing breeding in fishes using the said novel gonadotropin releasing hormones.

Abstract: A method for diagnosing process parameter variations from measurements in analog circuits. The diagnosability conditions for the accurate computation of device parameters are extended in the presence of measurement noise. In case this diagnosability condition is not met by standard test signals, a method is provided for automatically generating optimized tests that enable the computation of device parameters. The test generator explicitly optimizes the ability to compute device parameters from the test response. A cause-effect analysis engine is provided to diagnose the cause of variation in IC performance metrics in terms of the variation in device parameter values. Once the cause of parametric yield loss is diagnosed in terms of device parameters variations, the information can be used by process engineers to tune the manufacturing process to improve yield.

Abstract: A method for testing a system on a chip or a system on a package (““SOPC”) having a plurality of internal modules that are tested to determine whether predetermined performance specifications are satisfied. A first module of the SOPC is selected for testing. A determination is made as to whether the first module is directly accessible or not. If the first module is directly accessible, the module may be tested with automated test equipment external to the SOPC. If the first module is not directly accessible, the module may be tested with a second and third module of the SOPC.

Abstract: Systems and methods for digital-based, standards-compatible, testing of analog circuits embedded inside integrated circuits. In this regard, one such system can be broadly described by a test stimulus generator that transmits a binary-level test-stimulus signal into an analog circuit located inside an integrated circuit; a converter that converts an analog output signal from the analog circuit into a digital output signal; a boundary-scan register chain that transmits the digital output signal out of the integrated circuit, and a test equipment that receives the digital output signal using the IEEE 1149.1 boundary-scan standard and analyzes the digital output signal to compute one or more specifications of the analog circuit located inside the integrated circuit.

Abstract: A method and system for making optimal estimates of linearity metrics of analog-to-digital converters. A model building phase and a production test strategy are employed. During the model-building phase, a linear model an analog-to-digital converter is constructed from a set of accurately measured transition code voltages for a set of training analog-to-digital converters. During a production test of an individual analog-to-digital converter, a ramp test signal is applied to the individual analog-to-digital converter, a histogram of codes is produced, and the transition code voltages for the individual analog-to-digital converter are estimated from the resulting histogram. Linearity characteristics of the individual analog-to-digital converter may then be computed.

Abstract: A method and apparatus for high-resolution jitter measurement. A signal generating circuit produces a period reference signal and applies the reference signal to a sampling input of an ADC. An output signal of a DUT is coupled to a clock input of the ADC, and the frequency of the reference signal is set to be equal to the frequency of the output signal of the DUT plus a fixed offset such that the code output provides a digital representation of a beat signal. The beat signal is defined by discrete sampling points representing at least ten periods of the beat signal. Each period of the beat signal comprises a respective subset of the sampling points, wherein the sampling points of each of the subsets correspond to unique sampling phases that are defined similarly for each of the periods of the beat signal by the offset. The sampling points of each of the subsets are subject to variation from the corresponding sampling phases as a result of the jitter.

Abstract: A low cost signature test for RF and analog circuits. A model is provided to predict one or more performance parameters characterizing a first electronic circuit produced by a manufacturing process subject to process variation from the output of one or more second electronic circuits produced by the same process in response to a selected test stimulus, and iteratively varying the test stimulus to minimize the error between the predicted performance parameters and corresponding measured values for the performance parameters, for determining an optimized test stimulus. A non-linear model is preferably constructed for relating signature test results employing the optimized test stimulus in manufacturing testing to circuit performance parameters.

Abstract: A method for diagnosing process parameter variations from measurements in analog circuits. The diagnosability conditions for the accurate computation of device parameters are extended in the presence of measurement noise. In case this diagnosability condition is not met by standard test signals, a method is provided for automatically generating optimized tests that enable the computation of device parameters. The test generator explicitly optimizes the ability to compute device parameters from the test response. A cause-effect analysis engine is provided to diagnose the cause of variation in IC performance metrics in terms of the variation in device parameter values. Once the cause of parametric yield loss is diagnosed in terms of device parameters variations, the information can be used by process engineers to tune the manufacturing process to improve yield.

Abstract: A method and system for making optimal estimates of linearity metrics of analog-to-digital converters. A model building phase and a production test strategy are employed. During the model-building phase, a linear model an analog-to-digital converter is constructed from a set of accurately measured transition code voltages for a set of training analog-to-digital converters. During a production test of an individual analog-to-digital converter, a ramp test signal is applied to the individual analog-to-digital converter, a histogram of codes is produced, and the transition code voltages for the individual analog-to-digital converter are estimated from the resulting histogram. Linearity characteristics of the individual analog-to-digital converter may then be computed.

Abstract: Low power linear digital signal processing circuits are fabricated based on a design synthesis process using activity metrics. The average activity value .theta..sub.i of all the input nodes of the circuit is determined. Architectural transformations of the circuit are performed in order to minimize the average activity value over all the nodes. The transformation resulting in the minimum activity value is the synthesized design used as the basis for fabricating a low power linear digital signal processing circuit.

Abstract: An auxiliary monolithic integrated circuit chip provides both buffer amplification and testing interfaces. Off-the-shelf monolithic integrated circuit chips can be connected into an electronics system using one of these auxiliary buffer chips before each input port and after each output port, to implement functional testing similar to that done on monolithic integrated circuit chips with built-in test circuitry.