Patents by Inventor Abhirup LAHIRI

Abhirup LAHIRI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9170595
    Abstract: A PTAT circuit includes a first, second, third, and fourth transistors plus a resistor. The first and second transistors have control terminals coupled to each other. The third and fourth transistors have control terminals coupled to each other. The third transistor sources a first current to the first transistor and the fourth transistor sources a second current to the second transistor. The resistor is coupled at a node to the second transistor. A current source circuit sources additional current into the node that is derived from the first and second currents. In one implementation, the additional current is a scaled mirror of the second current. In another implementation, the additional current is a scaled mirror of the sum of the first and second currents. An output current is obtained by mirroring one of the first-third currents. A band-gap output voltage is obtained by applying the additional current across a resistance.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: October 27, 2015
    Assignee: STMicroelectronics International N.V.
    Inventor: Abhirup Lahiri
  • Patent number: 9146574
    Abstract: A current mirror circuit provides a current to drive a load. A noise cancelling circuit is provided to keep the load current constant in spite of variations in the supply voltage. The noise cancelling circuit includes an auxiliary current path which branches from the load current path. The length-to-width ratios of transistors of the circuit are selected to provide the desired noise cancellation while maintaining device stability.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: September 29, 2015
    Assignee: STMicroelectronics International N.V.
    Inventors: Nitin Gupta, Abhirup Lahiri
  • Patent number: 9018987
    Abstract: A phase locked loop includes a voltage controlled oscillator and a frequency divider or frequency multiplier. The voltage controlled oscillator and the frequency divider/multiplier are coupled together in a stacked configuration. A drive current is supplied to the voltage controlled oscillator. The drive current passes from the voltage controlled oscillator to the frequency divider/multiplier, thereby driving the frequency divider/multiplier with the same drive current that was supplied to the voltage controlled oscillator.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: April 28, 2015
    Assignee: STMicroelectronics International N.V.
    Inventor: Abhirup Lahiri
  • Patent number: 9000857
    Abstract: A circuit generates a compensation signal that can remove noise in a VCO introduced by a supply signal (i.e., supply-side noise). The circuit includes two transistors connected in series. A resistor is connected between the gate of the first transistor and the supply signal, and a capacitor is connected between the gate of the second transistor and the supply signal. The circuit is designed so that the transconductance of one transistor is greater than or equal to twice the transconductance of a second transistor. The compensation signal is supplied through a capacitor, which compensates for capacitors in a VCO, to an internal supply node of the VCO. At the internal supply node, the compensation signal removes (or greatly reduces) the noise introduced by the supply signal noise, resulting in a less-noisy output signal from the VCO.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: April 7, 2015
    Assignee: STMicroelectronics International N.V.
    Inventors: Abhirup Lahiri, Nitin Gupta
  • Publication number: 20140368281
    Abstract: A circuit generates a compensation signal that can remove noise in a VCO introduced by a supply signal (i.e., supply-side noise). The circuit includes two transistors connected in series. A resistor is connected between the gate of the first transistor and the supply signal, and a capacitor is connected between the gate of the second transistor and the supply signal. The circuit is designed so that the transconductance of one transistor is greater than or equal to twice the transconductance of a second transistor. The compensation signal is supplied through a capacitor, which compensates for capacitors in a VCO, to an internal supply node of the VCO. At the internal supply node, the compensation signal removes (or greatly reduces) the noise introduced by the supply signal noise, resulting in a less-noisy output signal from the VCO.
    Type: Application
    Filed: June 17, 2013
    Publication date: December 18, 2014
    Inventors: Abhirup Lahiri, Nitin Gupta
  • Publication number: 20140247035
    Abstract: A current mirror circuit provides a current to drive a load. A noise cancelling circuit is provided to keep the load current constant in spite of variations in the supply voltage. The noise cancelling circuit includes an auxiliary current path which branches from the load current path. The length-to-width ratios of transistors of the circuit are selected to provide the desired noise cancellation while maintaining device stability.
    Type: Application
    Filed: March 4, 2013
    Publication date: September 4, 2014
    Applicant: STMicroelectronics International N.V.
    Inventors: Nitin GUPTA, Abhirup LAHIRI
  • Publication number: 20140103900
    Abstract: A PTAT circuit includes a first, second, third, and fourth transistors plus a resistor. The first and second transistors have control terminals coupled to each other. The third and fourth transistors have control terminals coupled to each other. The third transistor sources a first current to the first transistor and the fourth transistor sources a second current to the second transistor. The resistor is coupled at a node to the second transistor. A current source circuit sources additional current into the node that is derived from the first and second currents. In one implementation, the additional current is a scaled mirror of the second current. In another implementation, the additional current is a scaled mirror of the sum of the first and second currents. An output current is obtained by mirroring one of the first-third currents. A band-gap output voltage is obtained by applying the additional current across a resistance.
    Type: Application
    Filed: October 12, 2012
    Publication date: April 17, 2014
    Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventor: Abhirup Lahiri
  • Patent number: 8653898
    Abstract: An embodiment of a crystal oscillator circuit includes leakage-current compensation, transconductance enhancement, or both leakage-current compensation and transconductance enhancement. Such an oscillator circuit may draw a reduced operating current relative to a conventional oscillator circuit, and thus may be suitable for battery or other low-power applications.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: February 18, 2014
    Assignee: STMicroelectronics International N.V.
    Inventors: Abhirup Lahiri, Anurag Tiwari
  • Publication number: 20120161888
    Abstract: An embodiment of a crystal oscillator circuit includes leakage-current compensation, transconductance enhancement, or both leakage-current compensation and transconductance enhancement. Such an oscillator circuit may draw a reduced operating current relative to a conventional oscillator circuit, and thus may be suitable for battery or other low-power applications.
    Type: Application
    Filed: June 30, 2011
    Publication date: June 28, 2012
    Applicant: STMICROELECTRONICS PVT. LTD.
    Inventors: Abhirup LAHIRI, Anurag TIWARI