Patents by Inventor Abhishek Dube

Abhishek Dube has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200399784
    Abstract: Embodiments generally relate to methods for depositing silicon-phosphorous materials, and more specifically, relate to using silicon-phosphorous compounds in vapor deposition processes (e.g., epitaxy, CVD, or ALD) to deposit silicon-phosphorous materials. In one or more embodiments, a method for forming a silicon-phosphorous material on a substrate is provided and includes exposing the substrate to a deposition gas containing one or more silicon-phosphorous compounds during a deposition process and depositing a film containing the silicon-phosphorous material on the substrate. The silicon-phosphorous compound has the chemical formula [(R3-vHvSi)—(R2-wHwSi)n]xPHyR?z, where each instance of R and each instance of R? are independently an alkyl or a halogen, n is 0, 1, or 2; v is 0, 1, 2, or 3; w is 0, 1, or 2; x is 1, 2, or 3; y is 0, 1, or 2; z is 0, 1, or 2, and where x+y+z=3.
    Type: Application
    Filed: August 2, 2019
    Publication date: December 24, 2020
    Inventors: Errol Antonio C Sanchez, Mark J. Saly, Schubert Chu, Abhishek Dube, Srividya Natarajan
  • Patent number: 10789956
    Abstract: A device may receive a set of audio data files corresponding to a set of calls, wherein the set of audio data files includes digital representations of one or more segments of respective calls of the set of calls, and wherein the set of calls includes audio data relating to a particular industry. The device may receive a set of transcripts corresponding to the set of audio data files. The device may determine a plurality of text-audio pairs within the set of calls, wherein a text-audio pair, of the plurality of text-audio pairs, comprises: a digital representation of a segment a call of the set of calls, and a corresponding excerpt of text from the set of transcripts. The device may train, using a machine learning process, an industry-specific text-to-speech model, tailored for the particular industry, based on the plurality of text-audio pairs.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: September 29, 2020
    Assignee: Capital One Services, LLC
    Inventor: Abhishek Dube
  • Publication number: 20200258997
    Abstract: The present disclosure generally relates to methods for forming a semiconductor device, a semiconductor device, and a processing chamber. The method includes forming a source/drain region in a processing system, forming a doped semiconductor layer on the source/drain region in the processing system, forming a metal silicide layer, forming a dielectric material, forming a trench in the dielectric material, and filling the trench with a conductor. The source/drain region, the doped semiconductor layer, and the metal silicide layer are formed without breaking vacuum. A semiconductor device includes a plurality of layers, and the semiconductor device has reduced contact resistance. A processing system is configured to perform the method and form the semiconductor device.
    Type: Application
    Filed: January 27, 2020
    Publication date: August 13, 2020
    Inventors: Gaurav THAREJA, Xuebin LI, Abhishek DUBE, Yi-Chiau HUANG, Andy LO, Patricia M. LIU, Sanjay NATARAJAN, Saurabh CHOPRA
  • Publication number: 20200203490
    Abstract: Implementations of the present disclosure generally relate to methods for forming a transistor. More specifically, implementations described herein generally relate to methods for forming a source/drain contact. In one implementation, the method includes forming a trench in a dielectric material to expose a source/drain region of a transistor, performing a pre-clean process on the exposed source/drain region, forming a doped semiconductor layer on the source/drain region by an epitaxial deposition process, and fill the trench with a conductor. The doped semiconductor layer has a lower electrical resistance than the source/drain region due to a higher dopant concentration in the doped semiconductor layer. As a result, the contact resistance of the source/drain contact is reduced.
    Type: Application
    Filed: November 8, 2019
    Publication date: June 25, 2020
    Inventors: Gaurav THAREJA, Xuebin LI, Abhishek DUBE, Yi-Chiau HUANG, Tushar Vidyadhar MANDREKAR, Andy LO, Patricia M. LIU, Sanjay NATARAJAN, Saurabh CHOPRA
  • Publication number: 20200144397
    Abstract: Methods and apparatuses for processing substrates, such as during silicon-germanium pre-cleans, are provided. A method includes introducing the substrate into a processing system, where the substrate contains a plurality of silicon-containing (e.g., SiGe) fins and a contaminant disposed on the silicon-containing fins, and exposing the substrate to a plasma treatment to remove at least a portion of the contaminant disposed from the silicon-containing fins. The method also includes exposing the substrate to an oxidation treatment to produce an oxide layer on the silicon-containing fins and the remaining contaminant thereon, then exposing the substrate to a dry-clean treatment to remove the oxide layer and the remaining contaminant from the silicon-containing fins and produce a cleaned surface thereon, and depositing an epitaxial layer on the cleaned surface on the silicon-containing fins.
    Type: Application
    Filed: September 17, 2019
    Publication date: May 7, 2020
    Applicants: Applied Materials, Inc., Applied Materials, Inc.
    Inventors: Abhishek DUBE, Sheng-Chin KUNG, Malcolm BEVAN, Johanes SWENBERG
  • Publication number: 20200075332
    Abstract: A method of forming a silicon cap which comprises substantially no germanium atoms nor oxygen atoms is disclosed. Methods for controlling the oxidation of a silicon cap layer are also disclosed. Methods of forming a metal gate replacement which utilize the disclosed silicon cap and controlled oxidation are also disclosed.
    Type: Application
    Filed: September 3, 2019
    Publication date: March 5, 2020
    Inventors: Johanes F. Swenberg, Abhishek Dube, Steven C.H. Hung, Benjamin Colombeau
  • Publication number: 20200013878
    Abstract: A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.
    Type: Application
    Filed: July 3, 2019
    Publication date: January 9, 2020
    Inventors: Benjamin Colombeau, Tushar Mandrekar, Patricia M. Liu, Suketu Arun Parikh, Matthias Bauer, Dimitri R. Kioussis, Sanjay Natarajan, Abhishek Dube
  • Patent number: 10504723
    Abstract: A method of forming a film on a substrate having silicon surfaces and dielectric surfaces includes precleaning the substrate; applying an inhibitor species to the dielectric surfaces; and exposing the substrate to a precursor while maintaining a temperature of less than about 600 degrees Celsius.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: December 10, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Xuebin Li, Hua Chung, Flora Fong-Song Chang, Schubert S. Chu, Abhishek Dube
  • Publication number: 20190301011
    Abstract: Embodiments of the disclosure may provide a method and apparatus for cleaning an epi-chamber at a low temperature so that residues are quickly eliminated from a surface of the epi-chamber after a performing a low temperature epitaxial deposition process. Some of the benefits of the present disclosure include flowing a chlorine containing gas to an improved epi-chamber having UV capability to chlorinate and quickly remove the epitaxial deposition residues at a low cleaning process temperature. As such, residues are decreased or removed from the epi-chamber such that further processing may be performed.
    Type: Application
    Filed: March 27, 2019
    Publication date: October 3, 2019
    Inventors: Geetika BAJAJ, Prerna Sonthalia GORADIA, Robert Jan VISSER, Abhishek DUBE, Flora Fong-Song CHANG, Hua CHUNG
  • Publication number: 20190148131
    Abstract: Methods and apparatus for processing a substrate are described herein. Methods for passivating dielectric materials include forming alkyl silyl moieties on exposed surfaces of the dielectric materials. Suitable precursors for forming the alkyl silyl moieties include (trimethylsilyl)pyrrolidine, aminosilanes, and dichlorodimethylsilane, among others. A capping layer may be selectively deposited on source/drain materials after passivation of the dielectric materials. Apparatus for performing the methods described herein include a platform comprising a transfer chamber, a pre-clean chamber, an epitaxial deposition chamber, a passivation chamber, and an atomic layer deposition chamber.
    Type: Application
    Filed: January 15, 2019
    Publication date: May 16, 2019
    Inventors: Abhishek DUBE, Schubert S. CHU, Jessica S. KACHIAN, David THOMPSON, Jeffrey ANTHIS
  • Patent number: 10276688
    Abstract: A device comprising Si:As source and drain extensions and Si:As or Si:P source and drain features formed using selective epitaxial growth and a method of forming the same is provided. The epitaxial layers used for the source and drain extensions and the source and drain features herein are deposited by simultaneous film formation and film etching, wherein the deposited material on the monocrystalline layer is etched at a slower rate than deposition material deposited on non-monocrystalline location of a substrate. As a result, an epitaxial layer is deposited on the monocrystalline surfaces, and a layer is not deposited on non-monocrystalline surfaces of the same base material, such as silicon.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: April 30, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Xinyu Bao, Zhiyuan Ye, Flora Fong-Song Chang, Abhishek Dube, Xuebin Li, Errol Antonio C. Sanchez, Hua Chung, Schubert S. Chu
  • Patent number: 10199215
    Abstract: Methods and apparatus for processing a substrate are described herein. Methods for passivating dielectric materials include forming alkyl silyl moieties on exposed surfaces of the dielectric materials. Suitable precursors for forming the alkyl silyl moieties include (trimethylsilyl)pyrrolidine, aminosilanes, and dichlorodimethylsilane, among others. A capping layer may be selectively deposited on source/drain materials after passivation of the dielectric materials. Apparatus for performing the methods described herein include a platform comprising a transfer chamber, a pre-clean chamber, an epitaxial deposition chamber, a passivation chamber, and an atomic layer deposition chamber.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: February 5, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Abhishek Dube, Schubert S. Chu, Jessica S. Kachian, David Thompson, Jeffrey Anthis
  • Patent number: 10128110
    Abstract: Embodiments of the present disclosure generally relate to methods for forming a doped silicon epitaxial layer on semiconductor devices at increased pressure and reduced temperature. In one embodiment, the method includes heating a substrate disposed within a processing chamber to a temperature of about 550 degrees Celsius to about 800 degrees Celsius, introducing into the processing chamber a silicon source comprising trichlorosilane (TCS), a phosphorus source, and a gas comprising a halogen, and depositing a silicon containing epitaxial layer comprising phosphorus on the substrate, the silicon containing epitaxial layer having a phosphorus concentration of about 1×1021 atoms per cubic centimeter or greater, wherein the silicon containing epitaxial layer is deposited at a chamber pressure of about 150 Torr or greater.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: November 13, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Abhishek Dube, Xuebin Li, Yi-Chiau Huang, Hua Chung, Schubert S. Chu
  • Publication number: 20180286961
    Abstract: A device comprising Si:As source and drain extensions and Si:As or Si:P source and drain features formed using selective epitaxial growth and a method of forming the same is provided. The epitaxial layers used for the source and drain extensions and the source and drain features herein are deposited by simultaneous film formation and film etching, wherein the deposited material on the monocrystalline layer is etched at a slower rate than deposition material deposited on non-monocrystalline location of a substrate. As a result, an epitaxial layer is deposited on the monocrystalline surfaces, and a layer is not deposited on non-monocrystalline surfaces of the same base material, such as silicon.
    Type: Application
    Filed: February 14, 2018
    Publication date: October 4, 2018
    Inventors: Xinyu BAO, Zhiyuan YE, Flora Fong-Song CHANG, Abhishek DUBE, Xuebin LI, Errol Antonio C. SANCHEZ, Hua CHUNG, Schubert S. CHU
  • Publication number: 20180230624
    Abstract: The present disclosure generally relate to a cluster tool and methods for forming an epitaxial layer on a semiconductor device. In one implementation, the cluster tool includes a transfer chamber, a pre-clean chamber coupled to the transfer chamber, a plasma-cleaning chamber coupled to the transfer chamber, a deposition chamber coupled to the transfer chamber, an etch chamber coupled to the transfer chamber, and a thermal process chamber coupled to the transfer chamber.
    Type: Application
    Filed: February 6, 2018
    Publication date: August 16, 2018
    Inventors: Abhishek DUBE, Xuebin LI, Hua CHUNG, Flora Fong-Song CHANG
  • Publication number: 20180190489
    Abstract: A method of forming a film on a substrate having silicon surfaces and dielectric surfaces includes precleaning the substrate; applying an inhibitor species to the dielectric surfaces; and exposing the substrate to a precursor while maintaining a temperature of less than about 600 degrees Celsius.
    Type: Application
    Filed: July 27, 2017
    Publication date: July 5, 2018
    Inventors: Xuebin LI, Hua CHUNG, Flora Fong-Song CHANG, Schubert S. CHU, Abhishek DUBE
  • Publication number: 20180158682
    Abstract: Embodiments of the present disclosure generally relate to methods for forming a doped silicon epitaxial layer on semiconductor devices at increased pressure and reduced temperature. In one embodiment, the method includes heating a substrate disposed within a processing chamber to a temperature of about 550 degrees Celsius to about 800 degrees Celsius, introducing into the processing chamber a silicon source comprising trichlorosilane (TCS), a phosphorus source, and a gas comprising a halogen, and depositing a silicon containing epitaxial layer comprising phosphorus on the substrate, the silicon containing epitaxial layer having a phosphorus concentration of about 1×1021 atoms per cubic centimeter or greater, wherein the silicon containing epitaxial layer is deposited at a chamber pressure of about 150 Torr or greater.
    Type: Application
    Filed: January 29, 2018
    Publication date: June 7, 2018
    Inventors: Abhishek Dube, Xuebin Li, Yi-Chiau Huang, Hua Chung, Schubert S. Chu
  • Patent number: 9929055
    Abstract: Implementations of the present disclosure generally relate to methods for epitaxial growth of a silicon material on an epitaxial film. In one implementation, the method includes forming an epitaxial film over a semiconductor fin, wherein the epitaxial film includes a top surface having a first facet and a second facet, and forming an epitaxial layer on at least the top surface of the epitaxial film by alternatingly exposing the top surface to a first precursor gas comprising one or more silanes and a second precursor gas comprising one or more chlorinated silanes at a temperature of about 375° C. to about 450° C. and a chamber pressure of about 5 Torr to about 20 Torr.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: March 27, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Abhishek Dube, Hua Chung, Jenn-Yue Wang, Xuebin Li, Yi-Chiau Huang, Schubert S. Chu
  • Patent number: 9923081
    Abstract: A device comprising Si:As source and drain extensions and Si:As or Si:P source and drain features formed using selective epitaxial growth and a method of forming the same is provided. The epitaxial layers used for the source and drain extensions and the source and drain features herein are deposited by simultaneous film formation and film etching, wherein the deposited material on the monocrystalline layer is etched at a slower rate than deposition material deposited on non-monocrystalline location of a substrate. As a result, an epitaxial layer is deposited on the monocrystalline surfaces, and a layer is not deposited on non-monocrystalline surfaces of the same base material, such as silicon.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: March 20, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Xinyu Bao, Zhiyuan Ye, Flora Fong-Song Chang, Abhishek Dube, Xuebin Li, Errol Antonio C. Sanchez, Hua Chung, Schubert S. Chu
  • Publication number: 20180047569
    Abstract: Embodiments of the present disclosure generally relate to methods for trench filling of high quality epitaxial silicon-containing material without losing selectivity of growth to dielectrics such as silicon oxides and silicon nitrides. The methods include epitaxially growing a silicon-containing material within a trench formed in a dielectric layer by exposing the trench to a gas mixture comprising a halogenated silicon compound and a halogenated germanium compound. In one embodiment, the halogenated silicon compound includes chlorinated silane and halogenated germanium compound includes chlorinated germane.
    Type: Application
    Filed: October 26, 2017
    Publication date: February 15, 2018
    Inventors: Yi-Chiau HUANG, Hua CHUNG, Abhishek DUBE