Abstract: Embodiments of the present disclosure relate to multi-flow gas circuits, processing chambers, and related apparatus and methods applicable for semiconductor manufacturing. In one or more embodiments, a processing chamber includes a chamber body, one or more heat sources, and a gas circuit in fluid communication with the chamber body. The gas circuit includes a first flow controller and a first set of valves in fluid communication with the first flow controller. The first set of valves are in fluid communication with a first set of inject passages. The gas circuit includes a second flow controller and a second set of valves in fluid communication with the second flow controller. The second set of valves is in fluid communication with a second set of inject passages. The second set of inject passages and the first set of inject passages alternate with respect to each other along the plurality of flow levels.

Abstract: Embodiments of the present disclosure relate to multi-flow methods and related apparatus applicable for semiconductor manufacturing. In one or more embodiments, a method of substrate processing includes flowing a first gas flow into a first set of flow levels of a processing chamber, and flowing a second gas flow into a second set of flow levels of the processing chamber simultaneously with the flowing of the first gas flow. The first set of flow levels and the second set of flow levels alternate with respect to each other. The method includes heating one or more substrates positioned in the processing chamber.

Abstract: The present disclosure relates to semiconductor processing methods for anisotropic film growth. The method includes heating a substrate positioned in a processing chamber. The method includes flowing one or more process gases over the substrate. The one or more process gases include trichlorosilane (TCS) and hydrochloric acid. The method includes depositing one or more layers on one or more fins on the substrate. The deposition of the one or more layers includes forming the one or more layers at a first growth rate along a first dimension and a second growth rate along a second dimension, and the second growth rate is faster than the first growth rate.

Abstract: Embodiments of the present disclosure relate to chamber kits, processing chambers, and related methods and components for gas activation applicable for semiconductor manufacturing. In one or more embodiments, a processing chamber includes a chamber body and one or more heat sources configured to heat a processing volume of the chamber body. The chamber body includes one or more gas inject passages formed in the chamber body, and one or more gas exhaust passages formed in the chamber body. The processing chamber includes a first pre-heat ring that includes a first opaque surface, and a second pre-heat ring that includes a second opaque surface. The first pre-heat ring and the second pre-heat ring define a first gas flow path between the first opaque surface and the second opaque surface, and the first gas flow path in fluid communication with at least one of the one or more gas inject passages.

Abstract: A semiconductor device and a method for manufacturing thereof. A substrate is provided. One or more groups of layers are formed on top of the substrate. A compensation layer is formed on top of at least one group of layers. At least one silicon layer is formed on top of the compensation layer. At least a portion of one or more layers in the one or more groups of layers is etched. The semiconductor device is formed.

Abstract: Semiconductor devices and methods for manufacturing the same are provided. The method includes epitaxially growing a doped crystalline silicon-containing layer over a source/drain feature and growing a doped amorphous silicon-containing layer over a field region of a semiconductor layer. The trench is formed in the semiconductor layer and the trench exposes the source/drain feature. The method further includes epitaxially growing an undoped crystalline silicon-containing capping layer over the doped crystalline silicon-containing layer and growing an undoped amorphous silicon-containing layer over the doped silicon-containing amorphous layer. The method further includes selectively removing the doped amorphous silicon-containing layer and the undoped amorphous silicon-containing layer relative to the silicon-containing crystalline capping layer. The method further includes removing the silicon-containing crystalline capping layer to expose the doped silicon-containing crystalline layer.

Abstract: A three-dimensional semiconductor (3D) device. The 3D device may include a substrate, and a monocrystalline layer stack. The monocrystalline layer stack may include at least one monocrystalline semiconductor layer, separated from, and disposed over a main surface of the substrate. The 3D device may further include a plurality of epitaxial heterostructures, integrally grown from the at least one monocrystalline semiconductor layer. As such, a first epitaxial heterostructure may be disposed on a lower surface of the at least one monocrystalline semiconductor layer, facing the substrate, and wherein a second epitaxial heterostructure may be disposed on an upper surface of the monocrystalline semiconductor layer, opposite the lower surface.

Abstract: In some implementations, a device may obtain, based on a characteristic associated with an account, a set of forecasted values from a dataset of forecasted values. The set of forecasted values may include forecasted values for a plurality of forecasting metrics for a plurality of time periods. The device may generate, for the account, feature metric values, for the plurality of time periods, for a plurality of feature metrics based on the set of forecasted values. The device may compute, for the account, at least one present or future value metric based on the feature metric values for the plurality of feature metrics.

Abstract: A method for the selective formation of epitaxial layers is described herein. In the method, epitaxial layers are deposited to form source and drain regions around a horizontal gate all around (hGAA structure). The method includes co-flowing a combination of chlorinated silicon containing precursors, antimony containing precursors, and n-type dopant precursors. The resulting source and drain regions are selectively grown from crystalline nanosheets or nanowires of the hGAA structure over the non-crystalline gate structure and dielectric layers. The source and drain regions are predominantly grown in a <110> direction.

Abstract: The present disclosure relates to methods of correlating zones of processing chambers, and related systems and methods. In one implementation, a method of correlating zones of a processing chamber includes partitioning the processing volume into a plurality of zones along a first direction of the processing volume and a second direction of the processing volume. The second direction intersects the first direction. The plurality of zones have a first zone number (m), and a second zone number (n). The method includes determining a group number. The determining of the group number includes multiplying a first value by a second value. The first value correlates to a first zone number (m) of a plurality of zones and the second value correlates to a second zone number (n) of the plurality of zones. The method includes grouping the zones into groups having a number that is equal to the group number.

Abstract: Methods for selectively depositing an epitaxial layer are provided. In some implementations, the selective epitaxial deposition process includes providing the co-flow of chlorosilane precursors with at least one of an antimony-containing precursor and a phosphorous-containing precursor. The method utilizes co-flowing of multiple chlorosilane precursors to enable combination of silicon and at least one of phosphorous and antimony in the same matrix using a low-temperature selective process. The deposited epitaxial layer using the epitaxial deposition techniques described not only contains phosphorous and/or antimony but also has a high activated phosphorous and/or antimony concentration.

Abstract: A semiconductor structure includes a stack of alternating doped semiconductor epitaxial layers and cap epitaxial layers formed on a substrate. Each doped semiconductor epitaxial layer includes silicon having carrier dopants, and each cap epitaxial layer includes silicon and carbon un-doped with carrier dopants.

Abstract: In some implementations, a device may obtain, based on a characteristic associated with an account, a set of forecasted values from a dataset of forecasted values. The set of forecasted values may include forecasted values for a plurality of forecasting metrics for a plurality of time periods. The device may generate, for the account, feature metric values, for the plurality of time periods, for a plurality of feature metrics based on the set of forecasted values. The device may compute, for the account, at least one present or future value metric based on the feature metric values for the plurality of feature metrics.

Abstract: One or more embodiments described herein relate to selective methods for fabricating devices and structures. In these embodiments, the devices are exposed inside the process volume of a process chamber. Precursor gases are flowed in the process volume at certain flow ratios and at certain process conditions. The process conditions described herein result in selective epitaxial layer growth on the {100} planes of the crystal planes of the devices, which corresponds to the top of each of the fins. Additionally, the process conditions result in selective etching of the {110} plane of the crystal planes, which corresponds to the sidewalls of each of the fins. As such, the methods described herein provide a way to grow or etch epitaxial films at different crystal planes. Furthermore, the methods described herein allow for simultaneous epitaxial film growth and etch to occur on the different crystal planes.

Abstract: A method and apparatus for forming strain relaxed buffers that may be used in semiconductor devices incorporating superlattice structures are provided. The method includes epitaxially depositing a first silicon germanium layer over the substrate. The first silicon germanium layer has a first surface that contacts a frontside surface of the substrate and a second surface opposite the first surface. The first silicon germanium layer has a first thickness and a germanium concentration gradient that increases from the first surface to the second surface. The method further includes epitaxially depositing a silicon germanium capping layer on the first silicon germanium layer. The silicon germanium capping layer has a second thickness and a substantially uniform germanium concentration that is equal to, substantially equal to, or greater than a maximum germanium concentration of the germanium concentration gradient.

Abstract: The present disclosure relates to batch processing apparatus, systems, and related methods and structures for epitaxial deposition operations. In one implementation, an apparatus for substrate processing includes a chamber body. The chamber body includes a processing volume, a plurality of gas inject passages, and an exhaust port. The apparatus includes one or more upper heat sources positioned above the processing volume, one or more lower heat sources positioned below the processing volume, and a pedestal assembly positioned in the processing volume. The apparatus includes one or more side heat sources positioned outwardly of the processing volume and configured to heat the processing volume through a side of the processing volume. The chamber body can be a dual-chamber body that includes a second processing volume, and the one or more side heat sources can be positioned outwardly of one or more of the processing volume or the second processing volume.

Abstract: Silicon germanium (SiGe)/silicon containing superlattice structure and methods for forming the same are provided. Various embodiments utilize SiGe layers in a SiGe/Si superlattice structure, which include varying concentrations of germanium throughout the layer to achieve reduced dislocations or a dislocation-free superlattice. For example, in some embodiments, for each SiGe layer there is a core SiGe film with a low Ge content and two thinner SiGe layers or cladding layers positioned on opposing sides of the core SiGe film with each of the SiGe cladding layers having a higher Ge content then the core SiGe film. Various embodiments provide for SiGe layers having a germanium depth profile enabling strained SiGe superlattice deposition on Si{110} substrates.

Abstract: A method for the selective formation of epitaxial layers is described herein. In the method, epitaxial layers are deposited to form source and drain regions around a horizontal gate all around (hGAA structure). The method includes co-flowing a combination of chlorinated silicon containing precursors, antimony containing precursors, and n-type dopant precursors. The resulting source and drain regions are selectively grown from crystalline nanosheets or nanowires of the hGAA structure over the non-crystalline gate structure and dielectric layers. The source and drain regions are predominantly grown in a <110> direction.

Abstract: Embodiments generally relate to methods for depositing silicon-phosphorous materials, and more specifically, relate to using silicon-phosphorous compounds in vapor deposition processes (e.g., epitaxy, CVD, or ALD) to deposit silicon-phosphorous materials. In one or more embodiments, a method for forming a silicon-phosphorous material on a substrate is provided and includes exposing the substrate to a deposition gas containing one or more silicon-phosphorous compounds during a deposition process and depositing a film containing the silicon-phosphorous material on the substrate. The silicon-phosphorous compound has the chemical formula [(R3-vHvSi)—(R2-wHwSi)n]xPHyR?z, where each instance of R and each instance of R? are independently an alkyl or a halogen, n is 0, 1, or 2; v is 0, 1, 2, or 3; w is 0, 1, or 2; x is 1, 2, or 3; y is 0, 1, or 2; z is 0, 1, or 2, and where x+y+z=3.

Abstract: Embodiments generally relate to methods for depositing silicon-phosphorous materials, and more specifically, relate to using silicon-phosphorous compounds in vapor deposition processes (e.g., epitaxy, CVD, or ALD) to deposit silicon-phosphorous materials. In one or more embodiments, a method for forming a silicon-phosphorous material on a substrate is provided and includes exposing the substrate to a deposition gas containing one or more silicon-phosphorous compounds during a deposition process and depositing a film containing the silicon-phosphorous material on the substrate. The silicon-phosphorous compound has the chemical formula [(R3-vHvSi)—(R2-wHwSi)n]xPHyR?z, where each instance of R and each instance of R? are independently an alkyl or a halogen, n is 0, 1, or 2; v is 0, 1, 2, or 3; w is 0, 1, or 2; x is 1, 2, or 3; y is 0, 1, or 2; z is 0, 1, or 2, and where x+y+z=3.