Patents by Inventor Abhishek Dube
Abhishek Dube has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8551845Abstract: A method and structure are disclosed for increasing strain in a device, specifically an n-type field effect transistor (NFET) complementary metal-oxide-semiconductor (CMOS) device. Embodiments of this invention include growing an epitaxial layer, performing a cold carbon or cluster carbon pre-amorphization implantation to implant substitutional carbon into the epitaxial layer, forming a tensile cap over the epitaxial layer, and then annealing to recrystallize the amorphous layer to create a stress memorization technique (SMT) effect. The epitaxial layer will therefore include substitutional carbon and have a memorized tensile stress induced by the SMT. Embodiments of this invention can also include a lower epitaxial layer under the epitaxial layer, the lower epitaxial layer comprising for example, a silicon carbon phosphorous (SiCP) layer.Type: GrantFiled: September 21, 2010Date of Patent: October 8, 2013Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Abhishek Dube, Viorel C. Ontalus
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Patent number: 8546204Abstract: A method for forming a conformal buffer layer of uniform thickness and a resulting semiconductor structure are disclosed. The conformal buffer layer is used to protect highly-doped extension regions during formation of an epitaxial layer that is used for inducing mechanical stress on the channel region of transistors.Type: GrantFiled: October 3, 2011Date of Patent: October 1, 2013Assignee: International Business Machines CorporationInventors: Abhishek Dube, Jophy Stephen Koshy
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Patent number: 8492234Abstract: A method for forming a field effect transistor device includes forming a gate stack portion on a substrate, forming a spacer portion on the gates stack portion and a portion of the substrate, removing an exposed portion of the substrate, epitaxially growing a first silicon material on the exposed portion of the substrate, removing a portion of the epitaxially grown first silicon material to expose a second portion of the substrate, and epitaxially growing a second silicon material on the exposed second portion of the substrate and the first silicon material.Type: GrantFiled: June 29, 2010Date of Patent: July 23, 2013Assignees: International Business Machines Corporation, GlobalFoundries Inc.Inventors: Kevin K. Chan, Abhishek Dube, Eric C. Harley, Judson R. Holt, Viorel C. Ontalus, Kathryn T. Schonenberg, Matthew W. Stoker, Keith H. Tabakman, Linda R. Black
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Patent number: 8426265Abstract: A method of manufacturing a complementary metal oxide semiconductor (CMOS) circuit, in which the method includes a reactive ion etch (RIE) of a CMOS circuit substrate that forms recesses, the CMOS circuit substrate including: an n-type field effect transistor (n-FET) region; a p-type field effect transistor (p-FET) region; an isolation region disposed between the n-FET and p-FET regions; and a gate wire comprising an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate, in which the recesses are formed adjacent to sidewalls of a reduced thickness; growing silicon germanium (SiGe) in the recesses; depositing a thin insulator layer on the CMOS circuit substrate; masking at least the p-FET region; removing the thin insulator layer from an unmasked n-FET region and an unmasked portion of the isolation region; etching the CMOS circuit substrate with hydrogen chloride (HCl) to remove the SiGe from the recesses in the n-FET region; and gType: GrantFiled: November 3, 2010Date of Patent: April 23, 2013Assignees: International Business Machines Corporation, GlobalFoundries, Inc.Inventors: Bo Bai, Linda Black, Abhishek Dube, Judson R. Holt, Viorel C. Ontalus, Kathryn T. Schonenberg, Matthew W. Stoker, Keith H. Tabakman
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Patent number: 8421191Abstract: Semiconductor structures are disclosed that include at least one FET gate stack located on a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. Embedded stressor elements are located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each stressor element includes a lower layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy doped semiconductor material. At least one monolayer of dopant is located within the upper layer of each of the embedded stressor elements.Type: GrantFiled: June 26, 2012Date of Patent: April 16, 2013Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Abhishek Dube, Judson R. Holt, Jinghong Li, Joseph S. Newbury, Viorel Ontalus, Dae-Gyu Park, Zhengmao Zhu
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Patent number: 8415252Abstract: A metal interconnect structure provides high adhesive strength between copper atoms in a copper-containing structure and a self-aligned copper encapsulation layer, which is selectively deposited only on exposed copper surfaces. A lower level metal interconnect structure comprises a first dielectric material layer and a copper-containing structure embedded in a lower metallic liner. After a planarization process that forms the copper-containing structure, a material that forms Cu—S bonds with exposed surfaces of the copper-containing structure is applied to the surface of the copper-containing structure. The material is selectively deposited only on exposed Cu surfaces, thereby forming a self-aligned copper encapsulation layer, and provides a high adhesion strength to the copper surface underneath. A dielectric cap layer and an upper level metal interconnect structure can be subsequently formed on the copper encapsulation layer.Type: GrantFiled: January 7, 2010Date of Patent: April 9, 2013Assignee: International Business Machines CorporationInventors: Tien-Jen Cheng, Abhishek Dube, Zhengwen Li, Huilong Zhu
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Publication number: 20130082275Abstract: A method for forming a conformal buffer layer of uniform thickness and a resulting semiconductor structure are disclosed. The conformal buffer layer is used to protect highly-doped extension regions during formation of an epitaxial layer that is used for inducing mechanical stress on the channel region of transistors.Type: ApplicationFiled: October 3, 2011Publication date: April 4, 2013Applicant: International Business Machines CorporationInventors: ABHISHEK DUBE, Jophy Stephen Koshy
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Patent number: 8394712Abstract: A gate stack is formed on a silicon substrate, and source/drain extension regions are formed around the gate stack. A dielectric spacer is formed around the gate stack. A pair of trenches is formed around the gate stack and the dielectric spacer by an etch so that sidewalls of the source/drain extension regions are exposed. Within each trench, an n-doped silicon liner is deposited on the sidewalls of the trenches by a first selective epitaxy process so that the interface between the dielectric spacer and the source/drain extension region is covered. Within each trench, an n-doped single crystalline silicon-carbon alloy is subsequently deposited to fill the trench by a second selective epitaxy process. A combination of an n-doped single crystalline silicon liner and an n-doped single crystalline silicon-carbon alloy functions as embedded source/drain regions of an n-type field effect transistor (NFET), which applies a tensile stress to the channel of the transistor.Type: GrantFiled: May 5, 2011Date of Patent: March 12, 2013Assignee: International Business Machines CorporationInventors: Abhishek Dube, Viorel Ontalus
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Patent number: 8389352Abstract: Epitaxial deposition of silicon germanium in a semiconductor device is achieved without using masks. Nucleation delays induced by interactions with dopants present before deposition of the silicon germanium are used to determine a period over which an exposed substrate surface may be subjected to epitaxial deposition to form a layer of SiGe on desired parts with substantially no deposition on other parts. Dopant concentration may be changed to achieve desired thicknesses within preferred deposition times. Resulting deposited SiGe is substantially devoid of growth edge effects.Type: GrantFiled: February 11, 2011Date of Patent: March 5, 2013Assignee: International Business Machines CorporationInventors: Ashima B. Chakravarti, Abhishek Dube, Dominic J. Schepis
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Patent number: 8378424Abstract: A semiconductor substrate having transistor structures and test structures with spacing between the transistor structures smaller than the spacing between the test structures is provided. A first iteratively performed deposition and etch process includes: depositing a first doped epitaxial layer having a first concentration of a dopant over the semiconductor substrate, and etching the first doped epitaxial layer. A second iteratively performed deposition and etch process includes: depositing a second doped epitaxial layer having a second concentration of the dopant higher than the first concentration over the semiconductor substrate, and etching the second doped epitaxial layer. The first concentration results in a first net growth rate over the transistor structures and the second concentration results in a lower, second net growth rate over the test structures than the transistor structures, resulting in reduced pattern loading.Type: GrantFiled: August 30, 2012Date of Patent: February 19, 2013Assignee: International Business Machines CorporationInventors: Abhishek Dube, Viorel Ontalus, Kathryn T. Schonenberg, Zhengmao Zhu
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Patent number: 8361859Abstract: An embedded, strained epitaxial semiconductor material, i.e., an embedded stressor element, is formed at the footprint of at least one pre-fabricated field effect transistor that includes at least a patterned gate stack, a source region and a drain region. As a result, the metastability of the embedded, strained epitaxial semiconductor material is preserved and implant and anneal based relaxation mechanisms are avoided since the implants and anneals are performed prior to forming the embedded, strained epitaxial semiconductor material.Type: GrantFiled: November 9, 2010Date of Patent: January 29, 2013Assignee: International Business Machines CorporationInventors: Thomas N. Adam, Stephen W. Bedell, Abhishek Dube, Eric C. T. Harley, Judson R. Holt, Alexander Reznicek, Devendra K. Sadana, Dominic J. Schepis, Matthew W. Stoker, Keith H. Tabakman
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Patent number: 8354314Abstract: Epitaxial deposition of silicon germanium in a semiconductor device is achieved without using masks. Nucleation delays induced by interactions with dopants present before deposition of the silicon germanium are used to determine a period over which an exposed substrate surface may be subjected to epitaxial deposition to form a layer of SiGe on desired parts with substantially no deposition on other parts. Dopant concentration may be changed to achieve desired thicknesses within preferred deposition times. Resulting deposited SiGe is substantially devoid of growth edge effects.Type: GrantFiled: February 11, 2011Date of Patent: January 15, 2013Assignee: International Business Machines CorporationInventors: Ashima B. Chakravarti, Abhishek Dube, Dominic J. Schepis
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Publication number: 20130009277Abstract: A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.Type: ApplicationFiled: September 14, 2012Publication date: January 10, 2013Applicant: International Business Machines CorporationInventors: Abhishek Dube, Subramanian S. Iyer, Babar Ali Khan, Oh-jung Kwon, Junedong Lee, Paul C. Parries, Chengwen Pei, Gerd Pfeiffer, Ravi M. Todi, Geng Wang
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Publication number: 20130009211Abstract: Epitaxial deposition of silicon germanium in a semiconductor device is achieved without using masks. Nucleation delays induced by interactions with dopants present before deposition of the silicon germanium are used to determine a period over which an exposed substrate surface may be subjected to epitaxial deposition to form a layer of SiGe on desired parts with substantially no deposition on other parts. Dopant concentration may be changed to achieve desired thicknesses within preferred deposition times. Resulting deposited SiGe is substantially devoid of growth edge effects.Type: ApplicationFiled: September 14, 2012Publication date: January 10, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ashima B. Chakravarti, Abhishek Dube, Dominic J. Schepis
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Patent number: 8338279Abstract: A semiconductor substrate having transistor structures and test structures with spacing between the transistor structures smaller than the spacing between the test structures is provided. A first iteratively performed deposition and etch process includes: depositing a first doped epitaxial layer having a first concentration of a dopant over the semiconductor substrate, and etching the first doped epitaxial layer. A second iteratively performed deposition and etch process includes: depositing a second doped epitaxial layer having a second concentration of the dopant higher than the first concentration over the semiconductor substrate, and etching the second doped epitaxial layer. The first concentration results in a first net growth rate over the transistor structures and the second concentration results in a lower, second net growth rate over the test structures than the transistor structures, resulting in reduced pattern loading.Type: GrantFiled: March 30, 2011Date of Patent: December 25, 2012Assignee: International Business Machines CorporationInventors: Abhishek Dube, Viorel Ontalus, Kathryn T. Schonenberg, Zhengmao Zhu
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Publication number: 20120319110Abstract: A semiconductor substrate having transistor structures and test structures with spacing between the transistor structures smaller than the spacing between the test structures is provided. A first iteratively performed deposition and etch process includes: depositing a first doped epitaxial layer having a first concentration of a dopant over the semiconductor substrate, and etching the first doped epitaxial layer. A second iteratively performed deposition and etch process includes: depositing a second doped epitaxial layer having a second concentration of the dopant higher than the first concentration over the semiconductor substrate, and etching the second doped epitaxial layer. The first concentration results in a first net growth rate over the transistor structures and the second concentration results in a lower, second net growth rate over the test structures than the transistor structures, resulting in reduced pattern loading.Type: ApplicationFiled: August 30, 2012Publication date: December 20, 2012Inventors: Abhishek Dube, Viorel Ontalus, Kathryn T. Schonenberg, Zhengmao Zhu
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Publication number: 20120280251Abstract: A gate stack is formed on a silicon substrate, and source/drain extension regions are formed around the gate stack. A dielectric spacer is formed around the gate stack. A pair of trenches is formed around the gate stack and the dielectric spacer by an etch so that sidewalls of the source/drain extension regions are exposed. Within each trench, an n-doped silicon liner is deposited on the sidewalls of the trenches by a first selective epitaxy process so that the interface between the dielectric spacer and the source/drain extension region is covered. Within each trench, an n-doped single crystalline silicon-carbon alloy is subsequently deposited to fill the trench by a second selective epitaxy process. A combination of an n-doped single crystalline silicon liner and an n-doped single crystalline silicon-carbon alloy functions as embedded source/drain regions of an n-type field effect transistor (NFET), which applies a tensile stress to the channel of the transistor.Type: ApplicationFiled: May 5, 2011Publication date: November 8, 2012Applicant: International Business Machines CorporationInventors: ABHISHEK DUBE, Viorel Ontalus
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Patent number: 8298908Abstract: A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.Type: GrantFiled: February 11, 2010Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: Abhishek Dube, Subramanian S. Iyer, Babar Ali Khan, Oh-jung Kwon, Junedong Lee, Paul C. Parries, Chengwen Pei, Gerd Pfeiffer, Ravi M. Todi, Geng Wang
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Patent number: 8299535Abstract: Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack located on an upper surface of a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. The structure further includes embedded stressor elements located on opposite sides of the at least one FET gate stack and within the semiconductor substrate.Type: GrantFiled: June 25, 2010Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Abhishek Dube, Judson R. Holt, Jeffrey B. Johnson, Jinghong Li, Dae-Gyu Park, Zhengmao Zhu
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Publication number: 20120261717Abstract: Semiconductor structures are disclosed that include at least one FET gate stack located on a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. Embedded stressor elements are located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each stressor element includes a lower layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy doped semiconductor material. At least one monolayer of dopant is located within the upper layer of each of the embedded stressor elements.Type: ApplicationFiled: June 26, 2012Publication date: October 18, 2012Applicant: International Business Machines CorporationInventors: Kevin K. Chan, Abhishek Dube, Judson R. Holt, Jinghong Li, Joseph S. Newbury, Viorel Ontalus, Dae-Gyu Park, Zhengmao Zhu