Patents by Inventor Abhishek Pathak
Abhishek Pathak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11958474Abstract: A computer-implemented method comprises: continuously monitoring, by an assisted-driving (AD) system using a sensor, surroundings of a vehicle being controlled by a driver; detecting, by the AD system using the sensor, a parking spot that is available; planning, by the AD system and in response to detecting the parking spot, a trajectory for the vehicle to park in the parking spot; and generating a prompt to the driver, by the AD system and in response to detecting the parking spot, to have the AD system handle parking of the vehicle in the parking spot, the prompt performed before the vehicle reaches the parking spot.Type: GrantFiled: July 20, 2021Date of Patent: April 16, 2024Assignee: Atieva, Inc.Inventor: Abhishek Pathak
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Patent number: 11962565Abstract: A computing system is provided, including a processor and memory storing instructions that cause the processor to execute a domain name service (DNS) log analyzer configured to identify a container identifier associated with a DNS request and a destination IP address associated with a DNS response to the DNS request, using one or more DNS logs, a fleet management system record analyzer configured to identify a first service associated with the container identifier and a second service associated with the destination IP address, using one or more fleet management system logs, and a dependency map generator configured to generate a service-to-service dependency map between the identified first service and the identified second service.Type: GrantFiled: December 15, 2022Date of Patent: April 16, 2024Assignee: Microsoft Technology Licensing, LLCInventors: Abhishek Pathak, Sorabh Kumar Gandhi, Craig Henry Wittenberg, Ming Hao, Rohit Sanjay Galwankar, Vivek Sanjeev Tejwani
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Patent number: 11924162Abstract: A computing system is provided, including a processor and memory storing instructions that cause the processor to execute a domain name service (DNS) log analyzer configured to identify a container identifier associated with a DNS request and a destination IP address associated with a DNS response to the DNS request, using one or more DNS logs, a fleet management system record analyzer configured to identify a first service associated with the container identifier and a second service associated with the destination IP address, using one or more fleet management system logs, and a dependency map generator configured to generate a service-to-service dependency map between the identified first service and the identified second service.Type: GrantFiled: December 15, 2022Date of Patent: March 5, 2024Assignee: Microsoft Technology Licensing, LLCInventors: Abhishek Pathak, Sorabh Kumar Gandhi, Craig Henry Wittenberg, Ming Hao, Rohit Sanjay Galwankar, Vivek Sanjeev Tejwani
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Publication number: 20230156339Abstract: A method for generating a panoramic image using an electronic device is provided. The method includes obtaining a scene preview with an optimal wider view using a camera sensor(s) of the electronic device. The method includes analyzing the obtained scene preview to recommend an optimal traversal path. Further, the method includes capturing a plurality of frames using the optimal traversal path to generate the panoramic image. Further, the method includes storing the generated panoramic image.Type: ApplicationFiled: August 19, 2022Publication date: May 18, 2023Inventors: Sandeep SURI, Abhishek PATHAK, Chirag BANSAL, Abhijeet PADHY, Ram Pravesh SINGH
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Publication number: 20230023349Abstract: A computer-implemented method comprises: continuously monitoring, by an assisted-driving (AD) system using a sensor, surroundings of a vehicle being controlled by a driver; detecting, by the AD system using the sensor, a parking spot that is available; planning, by the AD system and in response to detecting the parking spot, a trajectory for the vehicle to park in the parking spot; and generating a prompt to the driver, by the AD system and in response to detecting the parking spot, to have the AD system handle parking of the vehicle in the parking spot, the prompt performed before the vehicle reaches the parking spot.Type: ApplicationFiled: July 20, 2021Publication date: January 26, 2023Applicant: Atieva, Inc.Inventor: Abhishek Pathak
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Patent number: 11521697Abstract: A row decoder located on one side of a memory array selectively drives word lines in response to a row address. A word line fault detection circuit located on an opposite side of the first memory array operates to detect an open word line fault between the opposed sides of the memory array. The word line fault detection circuit includes a first clamp circuit that operates to clamp the word lines to ground. An encoder circuit encodes signals on the word lines to generate an encoded address. The encoded address is compared to the row address by a comparator circuit which sets an error flag indicating the open word line fault has been detected if the encoded address does not match the row address.Type: GrantFiled: January 14, 2020Date of Patent: December 6, 2022Assignee: STMicroelectronics International, N.V.Inventors: Shishir Kumar, Abhishek Pathak
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Publication number: 20210253167Abstract: A steering control system comprises a processor and a memory. The memory includes instructions that, when executed by the processor, cause the processor to: determine a steering direction of a vehicle; determine a selected gear of the vehicle; generate a first steering control value based on the steering direction and the selected gear; selectively control steering of the vehicle based on the first steering control value; in response to the selected gear changing, generate a second steering control value based on the steering direction and a second selected gear; and selectively control steering of the vehicle based on the second steering control value.Type: ApplicationFiled: February 13, 2020Publication date: August 19, 2021Inventor: Abhishek Pathak
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Publication number: 20200243153Abstract: A row decoder located on one side of a memory array selectively drives word lines in response to a row address. A word line fault detection circuit located on an opposite side of the first memory array operates to detect an open word line fault between the opposed sides of the memory array. The word line fault detection circuit includes a first clamp circuit that operates to clamp the word lines to ground. An encoder circuit encodes signals on the word lines to generate an encoded address. The encoded address is compared to the row address by a comparator circuit which sets an error flag indicating the open word line fault has been detected if the encoded address does not match the row address.Type: ApplicationFiled: January 14, 2020Publication date: July 30, 2020Applicant: STMicroelectronics International, N.V.Inventors: Shishir KUMAR, Abhishek PATHAK
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Patent number: 10706915Abstract: A memory device includes first and second dummy word line portions. A dummy word line driver drives the first dummy word line portion. A voltage dropping circuit causes a voltage on the second dummy word line to be less than a voltage on the first dummy word line. At least one dummy memory cell is coupled to the second dummy word line portion, remains in standby until assertion of the second dummy word line, and performs a dummy cycle in response to assertion of the second dummy word line. A reset signal generation circuit generates a reset signal in response to completion of a dummy cycle by the at least one dummy memory cell. An internal clock signal is generated from an external clock signal and the reset signal and is used in performing a read and/or write cycle to a memory array.Type: GrantFiled: March 13, 2019Date of Patent: July 7, 2020Assignee: STMicroelectronics International N.V.Inventors: Abhishek Pathak, Tanmoy Roy, Shishir Kumar
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Publication number: 20190285303Abstract: A control for a climate control system that serves a space that is also served by a wireless communication network, includes a wireless communication system for communicating with the wireless communication network; and a processor accepting information about the devices connected to the wireless communication network received via the wireless communication system and executing a climate control program that controls the HVAC system based upon information about the devices connected to the wireless communication network.Type: ApplicationFiled: July 12, 2018Publication date: September 19, 2019Inventor: Abhishek Pathak
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Patent number: 10418095Abstract: A memory circuit includes a wordline, memory cells connected to the wordline and a wordline driver circuit. The memory circuit further includes a read assist circuit including an n-channel pull-down transistor having a source-drain path connected between the wordline and a ground node. A bias circuit applies a biasing voltage to the gate terminal of the n-channel pull-down transistor that is modulated responsive to process, voltage and temperature conditions in order to provide controlled word line underdrive.Type: GrantFiled: May 14, 2018Date of Patent: September 17, 2019Assignee: STMicroelectronics International N.V.Inventor: Abhishek Pathak
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Publication number: 20190279707Abstract: A memory device includes first and second dummy word line portions. A dummy word line driver drives the first dummy word line portion. A voltage dropping circuit causes a voltage on the second dummy word line to be less than a voltage on the first dummy word line. At least one dummy memory cell is coupled to the second dummy word line portion, remains in standby until assertion of the second dummy word line, and performs a dummy cycle in response to assertion of the second dummy word line. A reset signal generation circuit generates a reset signal in response to completion of a dummy cycle by the at least one dummy memory cell. An internal clock signal is generated from an external clock signal and the reset signal and is used in performing a read and/or write cycle to a memory array.Type: ApplicationFiled: March 13, 2019Publication date: September 12, 2019Applicant: STMicroelectronics International N.V.Inventors: Abhishek PATHAK, Tanmoy ROY, Shishir KUMAR
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Patent number: 10311944Abstract: A first transistor has a first conduction terminal coupled to a second bit line, a second conduction terminal coupled to a bit line node, and a control terminal biased by a second control signal. A second transistor has a first conduction terminal coupled to a second complementary bit line, a second conduction terminal coupled to a complementary bit line node, and a control terminal biased by the second control signal. A first replica transistor has a first conduction terminal coupled to the second bit line, a second conduction terminal coupled to the complementary bit line node, and a control terminal biased such that the first replica transistor is off. A second replica transistor has a first conduction terminal coupled to the second complementary bit line, a second conduction terminal coupled to the bit line node, and a control terminal biased such that the second replica transistor is off.Type: GrantFiled: July 2, 2018Date of Patent: June 4, 2019Assignee: STMicroelectronics International N.V.Inventors: Dhori Kedar Janardan, Abhishek Pathak, Shishir Kumar
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Patent number: 10283191Abstract: Disclosed herein is a memory circuit including a dummy word line driver driving a dummy word line, dummy memory cells coupled to a dummy bit line and a dummy complementary bit line, and a transmission gate coupled to the dummy word line to pass a word line signal from the dummy word line driver to an input of the dummy memory cells. A transistor is coupled to the dummy word line between the transmission gate and a pair of pass gates of a given one of the dummy memory cells closest to the transmission gate along the dummy word line. A reset signal output is coupled to the dummy complementary bit line. The transistor serves to lower a voltage on the dummy word line, and a reset signal indicating an end of a measured dummy cycle is generated at the reset signal output.Type: GrantFiled: March 9, 2018Date of Patent: May 7, 2019Assignee: STMicroelectronics International N.V.Inventors: Abhishek Pathak, Tanmoy Roy, Shishir Kumar
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Patent number: 10249363Abstract: A memory array has word lines and bit lines. A row decoder is operable to decode a row address and select a corresponding word line. A read-write clock generator is operable to generate a hold clock signal. An address clock generator receives a read address, a write address, a dual port mode control signal, a read chip select signal, and a write chip select signal. When operating in dual port mode, and when operating in a read mode, the address clock generator applies a read delay to the read address and outputs the read address, as delayed, to the row pre-decoder as the address in response to the hold clock signal.Type: GrantFiled: June 26, 2018Date of Patent: April 2, 2019Assignee: STMicroelectronics International N.V.Inventors: Harsh Rawat, Abhishek Pathak
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Publication number: 20190035454Abstract: A first transistor has a first conduction terminal coupled to a second bit line, a second conduction terminal coupled to a bit line node, and a control terminal biased by a second control signal. A second transistor has a first conduction terminal coupled to a second complementary bit line, a second conduction terminal coupled to a complementary bit line node, and a control terminal biased by the second control signal. A first replica transistor has a first conduction terminal coupled to the second bit line, a second conduction terminal coupled to the complementary bit line node, and a control terminal biased such that the first replica transistor is off. A second replica transistor has a first conduction terminal coupled to the second complementary bit line, a second conduction terminal coupled to the bit line node, and a control terminal biased such that the second replica transistor is off.Type: ApplicationFiled: July 2, 2018Publication date: January 31, 2019Applicant: STMicroelectronics International N.V.Inventors: Dhori Kedar Janardan, Abhishek Pathak, Shishir Kumar
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Publication number: 20180301186Abstract: A memory array has word lines and bit lines. A row decoder is operable to decode a row address and select a corresponding word line. A read-write clock generator is operable to generate a hold clock signal. An address clock generator receives a read address, a write address, a dual port mode control signal, a read chip select signal, and a write chip select signal. When operating in dual port mode, and when operating in a read mode, the address clock generator applies a read delay to the read address and outputs the read address, as delayed, to the row pre-decoder as the address in response to the hold clock signal.Type: ApplicationFiled: June 26, 2018Publication date: October 18, 2018Applicant: STMicroelectronics International N.V.Inventors: Harsh Rawat, Abhishek Pathak
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Publication number: 20180261278Abstract: A memory circuit includes a wordline, memory cells connected to the wordline and a wordline driver circuit. The memory circuit further includes a read assist circuit including an n-channel pull-down transistor having a source-drain path connected between the wordline and a ground node. A bias circuit applies a biasing voltage to the gate terminal of the n-channel pull-down transistor that is modulated responsive to process, voltage and temperature conditions in order to provide controlled word line underdrive.Type: ApplicationFiled: May 14, 2018Publication date: September 13, 2018Applicant: STMicroelectronics International N.V.Inventor: Abhishek Pathak
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Patent number: 10037794Abstract: A first transistor has a first conduction terminal coupled to a second bit line, a second conduction terminal coupled to a bit line node, and a control terminal biased by a second control signal. A second transistor has a first conduction terminal coupled to a second complementary bit line, a second conduction terminal coupled to a complementary bit line node, and a control terminal biased by the second control signal. A first replica transistor has a first conduction terminal coupled to the second bit line, a second conduction terminal coupled to the complementary bit line node, and a control terminal biased such that the first replica transistor is off. A second replica transistor has a first conduction terminal coupled to the second complementary bit line, a second conduction terminal coupled to the bit line node, and a control terminal biased such that the second replica transistor is off.Type: GrantFiled: July 26, 2017Date of Patent: July 31, 2018Assignee: STMicroelectronics International N.V.Inventors: Dhori Kedar Janardan, Abhishek Pathak, Shishir Kumar
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Patent number: 10032506Abstract: A memory array has word lines and bit lines. A row decoder is operable to decode a row address and select a corresponding word line. A read-write clock generator is operable to generate a hold clock signal. An address clock generator receives a read address, a write address, a dual port mode control signal, a read chip select signal, and a write chip select signal. When operating in dual port mode, and when operating in a read mode, the address clock generator applies a read delay to the read address and outputs the read address, as delayed, to the row pre-decoder as the address in response to the hold clock signal.Type: GrantFiled: December 12, 2016Date of Patent: July 24, 2018Assignee: STMicroelectronics International N.V.Inventors: Harsh Rawat, Abhishek Pathak