Abstract: Methods, apparatus, and processor-readable storage media for pairing multiple devices into a designated group for a communication session are provided herein. An example computer-implemented method includes processing, via at least a portion of multiple processing devices, information associated with a network in connection with one or more device pairing requests from one or more of the processing devices; implementing, via at least one the multiple processing devices, a pairing algorithm, wherein the pairing algorithm comprises searching for one or more of the processing devices, in accordance with one or more temporal values associated with the at least one processing device and at least one of the one or more device pairing requests corresponding thereto, and one or more pairing parameters; and automatically pairing, via the network and based on the pairing algorithm, the at least one processing device to one or more of the processing devices.

Abstract: Retrieving content items in response to a query in a way that increases user satisfaction and increases chances of users consuming a retrieved content item is not trivial. One retrieval strategy may include dividing the content items into buckets according to a dimension about the content items and retrieving a top K number of items from different buckets to balance semantic affinity and the dimension. Choosing an optimal K for different buckets for a given query can be a challenge. Reinforcement learning can be used to train and implement an agent model that can choose the optimal K for different buckets.

Abstract: Some embodiments provide a method for controlling flow processing by an edge cluster including a first edge machine set operating in a first location set of a public cloud and a second edge machine set operating in a second location set of the public cloud. A controller set configures first and second managed forwarding element (MFE) sets operating in the first and second location sets respectively, with first and second forwarding rule sets to respectively forward first and second flows sets to the first and second edge machine sets for performing services. The first forwarding rule set specifies a first network address set for the first edge machine set, and the second forwarding rule set specifies a second network address set for the second edge machine set. The controller set monitors each edge machine to determine whether it is available to perform the services.

Abstract: One embodiment provides a graphics processor comprising an interface to a system interconnect and a graphics processor coupled to the interface, the graphics processor comprising circuitry configured to compact sample data for multiple sample locations of a pixel, map the multiple sample locations to memory locations that store compacted sample data, the memory locations in a memory of the graphics processor, apply lossless compression to the compacted sample data, and update a compression control surface associated with the memory locations, the compression control surface to specify a compression status for the memory locations

Abstract: Examples disclosed herein include writing pages of data to blocks, the data associated with an operator; writing the blocks to a file based on a sequential arrangement of the data in the blocks; writing the file to a spill data store; and executing an instruction by programmable circuitry to batch read the blocks in sequential order from the spill data store to a local memory

Abstract: Retrieving content items in response to a query in a way that increases user satisfaction and increases chances of users consuming a retrieved content item is not trivial. One content item retrieval system can combine different retrieval strategies. The content item retrieval system can retrieve a number of content items using different retrieval strategies and combining the content items together as the final results of the search. A naïve approach is to show fixed numbers of content items retrieved using the different retrieval strategies for any query. User engagement can be improved if the numbers can be tuned or optimized for a given query. Reinforcement learning can be used to train and implement an agent model that can choose the optimal numbers of content items retrieved using different retrieval strategies for a given query.

Abstract: An example IC structure includes a first layer comprising a plurality of transistors; a second layer comprising a stack of layers of one or more insulator materials and conductive interconnect structures extending through the one or more insulator materials; a third layer comprising bonding pads, wherein the second layer is between the first layer and the third layer; and a via continuously extending between one of the bonding pads and one of the conductive interconnect structures in a bottom layer of the stack of layers or a conductive structure in the first layer, wherein the bottom layer is a layer of the stack of layers that is closer to the first layer than all other layers of the stack of layers.

Abstract: A brain control interface system for determining a baseline for detecting brain activity of a user is disclosed. The brain control interface system comprising: a brain control interface configured to detect brain signals indicative of brain activity of a user in an environment, a memory configured to store activities of the user associated with different light scenes, a processor configured to: select, from the activities stored in the memory, a first activity of the user, control one or more lighting devices according to a first light scene associated with the first activity, detect brain signals of the user while the first light scene is active, determine, based on the detected brain signals, a first baseline for the brain signals, and store an association between the first baseline and the first light scene and/or the first activity.

Abstract: Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive data dependencies for one or more tasks comprising one or more producer tasks executing on the first processing resource and one or more consumer tasks executing on the second processing resource and move a data output from one or more producer tasks executing on the first processing resource to a cache memory communicatively coupled to the second processing resource. Other embodiments may be described and claimed.

Abstract: Technologies for fiber array unit (FAU) lid designs are disclosed. In one embodiment, channels in the lid allow for suction to be applied to fibers that the lid covers, pulling the fibers into place in a V-groove. The suction can hold the fibers in place as the fiber array unit is mated with a photonic integrated circuit (PIC) die. Additionally or alternatively, channels can be on pitch, allowing for pulling the FAU towards a PIC die as well as sensing the position and alignment of the FAU to the PIC die. In another embodiment, a warpage amount of a PIC die is characterized, and a FAU lid with a similar warpage is fabricated, allowing for the FAU to position fibers correctly relative to waveguides in the PIC die. In another embodiment, a FAU has an extended lid, which can provide fiber protection as well as position and parallelism tolerance control.

Abstract: Embodiments are generally directed to cache structure and utilization. An embodiment of an apparatus includes one or more processors including a graphics processor; a memory for storage of data for processing by the one or more processors; and a cache to cache data from the memory; wherein the apparatus is to provide for dynamic overfetching of cache lines for the cache, including receiving a read request and accessing the cache for the requested data, and upon a miss in the cache, overfetching data from memory or a higher level cache in addition to fetching the requested data, wherein the overfetching of data is based at least in part on a current overfetch boundary, and provides for data is to be prefetched extending to the current overfetch boundary.

Abstract: An IC device may include memory layers over a logic layer. A memory layer includes memory arrays, each of which includes memory cells arranged in rows and columns. A row of memory cells may be associated with a word line. A column of memory cells may be associated with a bit line. Bit lines of different memory arrays may be coupled using one or more vias or source/drain electrodes of transistors in the memory arrays. Alternatively, word lines of different memory arrays may be coupled using one or more vias or gate electrodes of transistors in the memory arrays. The logic layer has a logic circuit that can control data read operations and data write operations of the memory layers. The logic layer may include a power interconnect, which facilitates power delivery to the memory layers, and a signal interconnect, which facilitates signal transmission within the memory device.

Abstract: Aspects presented herein relate to methods and devices for frame processing including an apparatus, e.g., client or server. The apparatus may estimate a set of frame processing times for at least one first frame in a set of frames. The apparatus may also detect a set of actual frame processing times for the at least one first frame in the set of frames. The apparatus may also output, based on the set of estimated frame processing times and the set of actual frame processing times, an indication to adjust a set of second frame processing times for at least one second frame in the set of frames, where the at least one second frame is subsequent to the at least one first frame in the set of frames.

Abstract: The brain control interface system comprises: a brain control interface configured to detect brain signals indicative of brain activity of a user in an environment, an input configured to obtain data indicative of a current light scene of one or more lighting devices in the environment, a memory configured to store processing methods associated with different light scenes, one or more processor configured to: select, from the processing methods stored in the memory, a processing method in accordance with the current light scene, apply the selected processing method to obtain and/or process the brain signals, derive a control command and/or a mental state of the user from the brain signals, and control the controllable device based on the derived control command and/or the derived mental state.

Abstract: Methods, systems, and devices for wireless communications are described. A remote unit (RU) may transmit, to a distributed unit (DU), an indication of a skew time parameter associated with providing compensated samples for a plurality of symbols associated with a slot. The RU may store a set of samples associated with a first subset of the plurality of symbols associated with the slot, the storing based on a processing delay associated with receiving demodulation reference signals during a portion of the first subset of the plurality of symbols associated with the slot. The RU may transmit, to the DU, a burst of compensated samples for the plurality of symbols in a transmission window that is offset in time from a beginning symbol of the slot according to the skew time parameter.

Abstract: A system and method for monitoring and controlling assets to mitigate predicted future faults. The method includes receiving, by a processing circuit, data describing an asset from one or more data sources; generating, by the processing circuit, an asset data model based on the received data; receiving, by the processing circuit, an extensible data model describing an organizational structure of an enterprise associated with the asset; extending, by the processing circuit, the extensible data model to include the asset models executing, by the processing circuit, the extensible data model including the asset models to determine one or more key performance indicators for the asset; predicting, by the processing circuit, a future fault for the asset based on the key performance indicators; sending, by the processing circuit, an informed and prioritized notification to plant personnel regarding the predicted fault; and taking a corrective action to mitigate the predicted future fault.

Abstract: A system and method for monitoring and controlling energy use in an industrial process. The method includes: receiving, by a processing circuit, data describing energy use in an industrial process from one or more data sources; contextualizing, by the processing circuit, the data describing the energy use in an industrial process; generating, by the processing circuit, an energy data model based on the contextualized data; executing, by the processing circuit, the energy data model to determine key performance indicators for the energy use in an industrial process; displaying, by the processing circuit, the key performance indicators to a user; determining, by the processing circuit, if the key performance indicators are above one or more pre-determined thresholds; and taking a corrective action in response to the key performance indicators being above the one or more pre-determined thresholds.

Abstract: Techniques are described herein for detecting an invalid (e.g., spoof) email before it is received by an intended recipient. In some embodiments, the techniques may involve, upon receiving an electronic communication directed to an intended recipient, determining, based on information included in the electronic communication, a claimed source entity, and determining a domain associated with the email communication. The techniques may further involve determining an owner entity associated with the domain and then determining that the electronic communication is valid based on a comparison between the owner entity and the claimed source entity. Upon determining that the electronic communication is not valid, the techniques may further comprise performing one or more mitigation techniques.

Abstract: Embodiments described herein include software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. One embodiment provides techniques to optimize training and inference on a systolic array when using sparse data. One embodiment provides techniques to use decompression information when performing sparse compute operations. One embodiment enables the disaggregation of special function compute arrays via a shared reg file. One embodiment enables packed data compress and expand operations on a GPGPU. One embodiment provides techniques to exploit block sparsity within the cache hierarchy of a GPGPU.

Abstract: An IC device may include memory layers over a logic layer. A memory layer may include memory arrays and one or more peripheral circuits coupled to the memory arrays. A memory array may include memory cells arranged in rows and columns. A row of memory cells may be associated with a word line. A column of memory cells may be associated with a bit line. The logic layer includes one or more logic circuits that can control data read operations and data write operations of the memory layers. The logic layer may also include a power interconnect, which facilitates power delivery to the memory layers, and a signal interconnect, which facilitates signal transmission within the IC device. The IC device may further include vias that couple the memory layers to the logic layer. Each via may be connected to one or more memory layers and the logic layer.