Patents by Inventor Abhishek

Abhishek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250191405
    Abstract: A multi-modal articulation system translates human gestures into control commands for digital and automation devices. The system integrates a camera module, which captures facial and hand movements, with an image processing unit that extracts facial features, such as eyebrow movement, lip curvature, eyelid motion, and eye trajectory. These extracted features are analyzed in real time by an articulation recognition module that compares them against a database to recognize specific gestures. The system tracks and processes air-drawn hand gestures using a gesture trajectory tracking unit, which converts the motions into digital representations and classifies them using deep learning algorithms. The recognized gestures are converted into machine-readable control signals and executed on various connected devices via a relay control unit.
    Type: Application
    Filed: February 18, 2025
    Publication date: June 12, 2025
    Inventors: Rayed AL GHAMDI, Abhishek SHARMA, Sunil KUMAR SHARMA
  • Publication number: 20250188652
    Abstract: A method of manufacturing high bulk continuous multi-filament yarn comprises a number of distinct steps. In a first step, a plurality of filaments of polymer are melt spun to form a partially oriented yarn (POY). In a second step, the POYs are drawn and textured to form a draw textured yarn, wherein texturing is carried out in a friction texturing process. Subsequently at least two plies of the draw textured yarn are twisted and/or cabled together and subsequently heat set to obtain the high bulk continuous multifilament yarn.
    Type: Application
    Filed: April 18, 2023
    Publication date: June 12, 2025
    Inventor: Abhishek MANDAWEWALA
  • Publication number: 20250190969
    Abstract: Systems, methods, and computer program products are provided for flexible transaction message routing. An exemplary method includes receiving an authorization request message associated with a payment transaction. The authorization request message includes a first account identifier associated with a user. A second account identifier is determined from a plurality of account identifiers based on at least one rule associated with the first account identifier. A modified authorization request message for the payment transaction is generated. The modified authorization request message includes the second account identifier. The modified authorization request message is transmitted to an issuer system associated with the second account identifier. A transaction history record based on the payment transaction and the second account identifier is stored.
    Type: Application
    Filed: March 31, 2023
    Publication date: June 12, 2025
    Inventors: Conor John Lynch, Christopher Joseph Bishop, Karthikeyan Palanisamy, Emily Chang, C. William Byrne, III, Kaori Hirakawa, Abhishek Verma, Shipra Jha
  • Publication number: 20250190674
    Abstract: Some embodiments provide a method for performing pixel-based rule checking on a layout that is used in a process for designing or manufacturing an integrated circuit. This pixel-based method provides an optimal approach for performing rule checks for layouts having shapes with curvilinear contours (i.e., with curvilinear edges). This method in some embodiments performs the rule check on a per pixel-basis that is optimal for curvilinear edges on which one or more pixels reside. In some embodiments, the layout is a mask layout used to manufacture the IC, while in other embodiments, the layout is a design layout used to design the IC (e.g., a layout used during the physical design process).
    Type: Application
    Filed: October 21, 2024
    Publication date: June 12, 2025
    Inventors: Mariusz A. Niewczas, Yefim G. Belenky, Abhishek Shendre, Michael Pomerantsev, Akira Fujimura
  • Publication number: 20250191206
    Abstract: A method includes determining, based on an image having an initial viewpoint, a depth image, and determining a foreground visibility map including visibility values that are inversely proportional to a depth gradient of the depth image. The method also includes determining, based on the depth image, a background disocclusion mask indicating a likelihood that pixel of the image will be disoccluded by a viewpoint adjustment. The method additionally includes generating, based on the image, the depth image, and the background disocclusion mask, an inpainted image and an inpainted depth image. The method further includes generating, based on the depth image and the inpainted depth image, respectively, a first three-dimensional (3D) representation of the image and a second 3D representation of the inpainted image, and generating a modified image having an adjusted viewpoint by combining the first and second 3D representation based on the foreground visibility map.
    Type: Application
    Filed: February 24, 2025
    Publication date: June 12, 2025
    Inventors: Varun Jampani, Huiwen Chang, Kyle Sargent, Abhishek Kar, Richard Tucker, Dominik Kaeser, Brian L. Curless, David Salesin, William T. Freeman, Michael Krainin, Ce Liu
  • Publication number: 20250190182
    Abstract: A method and a system for automatically deploying a low-code no-code model are disclosed. The method includes receiving an input in at least one format. The method includes analyzing, using a trained model, the input to generate at least one recommendation. The method includes selecting at least one service from the service catalog database based on the generated at least one recommendation. The method includes generating an infrastructure script for the selected at least one service using an Infrastructure as Code (IAC) catalog database having a plurality of pre-defined IAC scripts. The method includes generating an application script for the generated infrastructure script using a code catalog database having a plurality of application scripts. The method includes generating an application code for deployment based on an integration of the selected at least one service and the generated application script.
    Type: Application
    Filed: January 25, 2024
    Publication date: June 12, 2025
    Applicant: JPMorgan Chase Bank, N.A.
    Inventors: Abhishek MITRA, Richa MALIK, Gaurav KARKAL, Radha JAYARAMAN, Parul VERMA, Shankhadeep ROY
  • Publication number: 20250189885
    Abstract: Some embodiments provide a method for performing pixel-based rule checking on a layout that is used in a process for designing or manufacturing an integrated circuit. This pixel-based method provides an optimal approach for performing rule checks for layouts having shapes with curvilinear contours (i.e., with curvilinear edges). This method in some embodiments performs the rule check on a per pixel-basis that is optimal for curvilinear edges on which one or more pixels reside. In some embodiments, the layout is a mask layout used to manufacture the IC, while in other embodiments, the layout is a design layout used to design the IC (e.g., a layout used during the physical design process).
    Type: Application
    Filed: October 21, 2024
    Publication date: June 12, 2025
    Inventors: Mariusz A. Niewczas, Yefim G. Belenky, Abhishek Shendre, Michael Pomerantsev, Akira Fujimura
  • Publication number: 20250190673
    Abstract: Some embodiments provide a method for performing pixel-based rule checking on a layout that is used in a process for designing or manufacturing an integrated circuit. This pixel-based method provides an optimal approach for performing rule checks for layouts having shapes with curvilinear contours (i.e., with curvilinear edges). This method in some embodiments performs the rule check on a per pixel-basis that is optimal for curvilinear edges on which one or more pixels reside. In some embodiments, the layout is a mask layout used to manufacture the IC, while in other embodiments, the layout is a design layout used to design the IC (e.g., a layout used during the physical design process).
    Type: Application
    Filed: October 21, 2024
    Publication date: June 12, 2025
    Inventors: Mariusz A. Niewczas, Yefim G. Belenky, Abhishek Shendre, Michael Pomerantsev, Akira Fujimura
  • Publication number: 20250189948
    Abstract: Some embodiments provide a method for performing pixel-based rule checking on a layout that is used in a process for designing or manufacturing an integrated circuit. This pixel-based method provides an optimal approach for performing rule checks for layouts having shapes with curvilinear contours (i.e., with curvilinear edges). This method in some embodiments performs the rule check on a per pixel-basis that is optimal for curvilinear edges on which one or more pixels reside. In some embodiments, the layout is a mask layout used to manufacture the IC, while in other embodiments, the layout is a design layout used to design the IC (e.g., a layout used during the physical design process).
    Type: Application
    Filed: October 21, 2024
    Publication date: June 12, 2025
    Inventors: Mariusz A. Niewczas, Yefim G. Belenky, Abhishek Shendre, Michael Pomerantsev, Akira Fujimura
  • Publication number: 20250193118
    Abstract: A destination station (STA) in a wireless network, comprising: a memory; and a processor coupled to the memory, the processor configured to: receive, from a source STA via a router, a plurality of packets, the router being located between the destination STA and a source STA; determine a congestion prediction to the source STA based on packet arrival times of the plurality of packets; compare the congestion prediction with a first threshold; generate a congestion prediction signal based on the comparison, wherein the congestion prediction signal indicates an operation mode of the source STA; and transmit, to the source STA via the router, the congestion prediction signal.
    Type: Application
    Filed: December 3, 2024
    Publication date: June 12, 2025
    Inventors: Kyeong Jin Kim, Abhishek Sehgal, Yuming Zhu, Neha Dawar
  • Publication number: 20250192099
    Abstract: Integrated circuit package having a substrate employing reduced area, added metal pad(s) to metal interconnect(s) to reduce a die to a substrate clearance and related fabrication methods are disclosed. The IC package includes die interconnects coupled to first metal pad(s) of respective metal interconnects of a metallization layer of the substrate to provide support and signal routing paths. To reduce clearance between the die and the substrate and consequently the height of the IC package, a second, additional metal pad(s) having a reduced cross-sectional area from the first metal pad(s) is coupled to the first metal pad(s). Solder is employed to couple the second, additional metal pad(s) to a die interconnect(s) of the die to couple the die to the substrate. When the solder is heated to form the solder joint, the solder flows along the reduced cross-sectional area of the second, additional metal pad(s).
    Type: Application
    Filed: December 6, 2023
    Publication date: June 12, 2025
    Inventors: Ashish Alawani, Abhishek Shrikant Agarwal, Heun Gun Shin
  • Patent number: 12327809
    Abstract: Described herein are three-dimensional memory arrays that include multiple layers of memory cells. The layers are stacked and bonded to each other at bonding interfaces. The layers are formed on a support structure, such as a semiconductor wafer, that is grinded down before the layers are bonded. Vias extend through multiple layers of memory cells, including through the support structures and bonding interfaces. Thinning the support structure enables a tighter via pitch, which reduces the portion of the footprint used for vias. The memory cells may include three-dimensional transistors with a recessed gate and extended channel length.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: June 10, 2025
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Wilfred Gomes, Mauro J. Kobrinsky
  • Patent number: 12327581
    Abstract: Integrated circuits with embedded memory that includes ferroelectric capacitors having first conductor structures coupled to an underlying array of access transistors, and second conductors coupled to independent plate lines that are shunted by a metal strap having a pitch similar to that of the capacitors. The independent plate lines may reduce bit-cell disturbs and/or simplify read/write process while the plate line straps reduce series resistance of the plate lines. The metal straps may be subtractively patterned lines in direct contact with the second capacitor conductors, or may be damascene structures coupled to the second capacitor conductors through vias that also have a pitch similar to that of the capacitors.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: June 10, 2025
    Assignee: Intel Corporation
    Inventors: Wilfred Gomes, Abhishek Anil Sharma, Uygar Avci
  • Patent number: 12326919
    Abstract: Systems, methods, tangible non-transitory computer-readable media, and devices for autonomous vehicle operation are provided. For example, a computing system can receive object data that includes portions of sensor data. The computing system can determine, in a first stage of a multiple stage classification using hardware components, one or more first stage characteristics of the portions of sensor data based on a first machine-learned model. In a second stage of the multiple stage classification, the computing system can determine second stage characteristics of the portions of sensor data based on a second machine-learned model. The computing system can generate an object output based on the first stage characteristics and the second stage characteristics. The object output can include indications associated with detection of objects in the portions of sensor data.
    Type: Grant
    Filed: April 29, 2022
    Date of Patent: June 10, 2025
    Assignee: AURORA OPERATIONS, INC.
    Inventors: Joseph Lawrence Amato, Nemanja Djuric, Shivam Gautam, Abhishek Mohta, Fang-Chieh Chou
  • Patent number: 12328946
    Abstract: Embodiments disclosed herein include semiconductor devices with electrostatic discharge (ESD) protection of the transistor devices. In an embodiment, a semiconductor device comprises a semiconductor substrate, where a transistor device is provided on the semiconductor substrate. In an embodiment, the semiconductor device further comprises a stack of routing layers over the semiconductor substrate, and a diode in the stack of routing layers. In an embodiment, the diode is configured to provide electrostatic discharge (ESD) protection to the transistor device.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: June 10, 2025
    Assignee: Intel Corporation
    Inventors: Urusa Alaan, Abhishek A. Sharma, Charles C. Kuo, Benjamin Orr, Nicholas Thomson, Ayan Kar, Arnab Sen Gupta, Kaan Oguz, Brian S. Doyle, Prashant Majhi, Van H. Le, Elijah V. Karpov
  • Publication number: 20250182018
    Abstract: There is a challenge in creating a seamless food supply chain that aligns with unique characteristics of each food item while considering business values. The present disclosure address the challenges associated with the food supply chain by providing a system and method for evaluating sustainability of a food supply chain network using digital twin. The present discourse describes developing a set of modeling abstractions and a digital twin-based approach to explore ideal supply chains for food, aiming to reduce food wastage, ensure food quality and improve profit margins. In the present disclosure, unique characteristics of fruit supply chains are described which are further applied to food supply chains. Using the characteristics of climacteric fruits, unique requirements that contemporary perishable food supply chains need to consider are described.
    Type: Application
    Filed: November 1, 2024
    Publication date: June 5, 2025
    Applicant: Tata Consultancy Services Limited
    Inventors: Abhishek YADAV, Souvik BARAT, Aditya Avinash PARANJAPE, Parijat Dilip DESHPANDE, Vinay KULKARNI, Beena RAI
  • Publication number: 20250180366
    Abstract: A system and method include providing a list of children to be picked up by a vehicle at a particular stop along a route to a driver device. The provided list is displayed as part of a graphical user interface which includes a plurality of pick up options for each child in the list of children. The options include a picked up interface button, a no show interface button and a canceled button. The graphical user interface provides a picture and identification of each child. The server device transmits a message to a user device with confirmation that a child has been picked up. The server device also provides a list of children to be dropped off by the vehicle via a graphical user interface that also provides drop off options for each child in the list of children including a dropped off button or an on hold button.
    Type: Application
    Filed: July 24, 2024
    Publication date: June 5, 2025
    Applicant: Zum Services, Inc.
    Inventors: Abhishek Garg, Alexey Kononov, Shiva Nagabushanaswamy, Sidi Liu, Andrew Mormysh, Sreejith Nair, Kanstantsin Gerasimovich, Rashmi Choudhary, Rohit Jain, Melissa Shiu, Niket Sanghvi, Lipi Sanghi
  • Publication number: 20250182709
    Abstract: Often when there is a glare on a display screen the user may be able to mitigate the glare by tilting or otherwise moving the screen or changing their viewing position. However, when driving a car there are limited options for overcoming glares on the dashboard, especially when you are driving for a long distance in the same direction. Embodiments are directed to eliminating such glare. Other embodiments are related to mixed reality (MR) and filling in occluded areas.
    Type: Application
    Filed: January 8, 2025
    Publication date: June 5, 2025
    Inventors: Arthur J. Runyan, Richmond Hicks, Nausheen Ansari, Narayan Biswal, Ya-Ti Peng, Abhishek R. Appu, Wen-Fu Kao, Sang-Hee Lee, Joydeep Ray, Changliang Wang, Satyanarayana Avadhanam, Scott Janus, Gary Smith, Nilesh V. Shah, Keith W. Rowe, Robert J. Johnston
  • Publication number: 20250182200
    Abstract: Methods and systems for a borrower identification and prediction of credit risk associated with the identified borrower is provided. The system includes a server that retrieves an electronic message that includes details of transactions conducted by a first entity over a time. The electronic message is parsed based on a predefined parameter, to identify a second entity, where the first entity has conducted a business transaction with the second entity. Further, a first set of details associated with the second entity is obtained from one or more resources associated with the server. Furthermore, a knowledge graph is generated based on the business transaction and the first set of details. The knowledge graph indicates an association between the first entity and the second entity. Subsequently, a credit risk score associated with lending money to the second entity is predicted based on the knowledge graph.
    Type: Application
    Filed: June 19, 2024
    Publication date: June 5, 2025
    Inventors: Harshvardhan Lunia, Vibhor Kalra, Giridhar Yasa, Manish Bhatia, Nitin Shiralkar, Prasanna Kumar, Amit Abhishek, Aditya Veluri
  • Publication number: 20250182294
    Abstract: Methods and systems for image segmentation include generating features at multiple scales from an input image using a backbone model. The features are encoded using a transformer encoder that creates a per-pixel embedding map from a high-resolution scale of the multiple scales using deformable attention layers that operate on progressively higher-resolution scales of the multiple scales. The features are decoded using a transformer decoder to generate a segmentation mask.
    Type: Application
    Filed: December 4, 2024
    Publication date: June 5, 2025
    Inventors: Abhishek Aich, Yumin Suh, Samuel Schulter