Abstract: A network function virtualization (NFV) orchestration service includes a centralized orchestration device and a multi-cluster container management (MCCM) platform. The centralized orchestration device stores a catalog of virtual network function descriptors (VNFDs) in an input language; generates, based on the catalog of VNFDs, intents for containerized network function (CNF) services; and stores the generated intents as blocks in a central intent database, wherein the blocks include an input data model for the CNF services. The MCCM platform includes one or more processors to receive and store a copy of the intent database; read design time policies from the copy of the intent database; and convert the input data model into a vendor-specific output data model in an output language.

Abstract: A system and method for monitoring and controlling production of batches of products in an industrial process, the method comprising: receiving, by a processing circuit, data describing a batch of products generated in an industrial process from one or more data sources; contextualizing, by the processing circuit, the data describing the batch of products generated in the industrial process; generating, by the processing circuit, a batch data model based on the contextualized data; executing, by the processing circuit, the batch data model to determine key performance indicators for the batch of products; comparing, by the processing circuit, the key performance indicators to pre-determined key performance indicators; and performing an automated action based on a result of the comparison.

Abstract: Apparatuses including a graphics processing unit, graphics multiprocessor, or graphics processor having an error detection correction logic for cache memory or shared memory are disclosed. In one embodiment, a graphics multiprocessor includes cache or local memory for storing data and error detection correction circuitry integrated with or coupled to the cache or local memory. The error detection correction circuitry is configured to perform a tag read for data of the cache or local memory to check error detection correction information.

Abstract: Apparatus and method for establishing a stable operating point of a H-bridge with a center shunt switch. The stable operating point lets a circuit connected to the H-bridge outputs work in a more ideal condition. As such, an H-bridge with a stable operating point will yield a higher performance and/or save power. Since common mode is one of the biggest sources of electromagnetic interference, a stable operating point in an H-bridge also suppresses EMI.

Abstract: A method includes determining, based on an image having an initial viewpoint, a depth image, and determining a foreground visibility map including visibility values that are inversely proportional to a depth gradient of the depth image. The method also includes determining, based on the depth image, a background disocclusion mask indicating a likelihood that pixel of the image will be disoccluded by a viewpoint adjustment. The method additionally includes generating, based on the image, the depth image, and the background disocclusion mask, an inpainted image and an inpainted depth image. The method further includes generating, based on the depth image and the inpainted depth image, respectively, a first three-dimensional (3D) representation of the image and a second 3D representation of the inpainted image, and generating a modified image having an adjusted viewpoint by combining the first and second 3D representation based on the foreground visibility map.

Abstract: An apparatus and method are described for managing data which is biased towards a processor or a GPU. For example, an apparatus comprises a processor comprising one or more cores, one or more cache levels, and cache coherence controllers to maintain coherent data in the one or more cache levels; a graphics processing unit (GPU) to execute graphics instructions and process graphics data, wherein the GPU and processor cores are to share a virtual address space for accessing a system memory; a GPU memory addressable through the virtual address space shared by the processor cores and GPU; and bias management circuitry to store an indication for whether the data has a processor bias or a GPU bias, wherein if the data has a GPU bias, the data is to be accessed by the GPU without necessarily accessing the processor's cache coherence controllers.

Abstract: A technique enables coordination of unrelated software components to facilitate extensive recovery point management on a snapshot or recovery point through the use of a flexible tag structure. The tag is organized and arranged as a {key=value,[value] . . . } structure wherein the key denotes an operation that requires coordination between the unrelated software components and the value(s) denote multi-cardinality that provide parameters for coordination of the operation. The multi-cardinality aspect of the flexible tag structure provides a set of values associated with the key of the tag that enables a software component and/or protocol to insert its value(s) into the tag structure for its interpretation. The technique thus provides an extensible model where multiple components/protocols use the tag to coordinate operations on the RP by conveying certain meaning/interpretations of the tag and its values.

Abstract: A system provides a framework for testing template code processed by a templating engine. A multitenant system may use template code for implementing Infrastructure as Code (IAC), for example, to generate pipelines for deploying software or provisioning resources for a datacenter configured in a cloud platform. The system sets the search path in a template engine environment object dynamically for each template file. The system allows testing of macros used by the template engine. The system converts the macros to callable entities that can be invoked by test cases. The system allows developers to finding code defects earlier and increase application availability. The system provides flexibility in testing and automation in running the tests. Furthermore, the system allows a separation of production code with unit tests.

Abstract: A power converter apparatus includes a parent circuit board comprising a first surface, a second surface, and a thermal conductor core disposed intermediate the first surface and the second surface. A first child circuit is board mounted on the parent circuit board. A first plurality of power switches are mounted on the first child circuit board. A second child circuit is board mounted on the parent circuit board. A second plurality of power switches are mounted on the second child circuit board. A first heat transfer circuit includes a first set of conductors thermally conductively coupling the first plurality of power switches with the thermal conductor core. A second heat transfer circuit includes a second set of conductors thermally conductively coupling the second plurality of power switches with the thermal conductor core.

Abstract: An example method involves providing an interface that simultaneously displays an indication of a respective volume corresponding to each of at least two zone players and displays a respective selectable icon corresponding to each of the at least two zone players. Each respective selectable icon indicates whether the corresponding zone player has been selected for a group, and at least one of the respective selectable icons indicates that a respective zone player has been selected for the group. The interface further displays an indication of a group volume associated with the at least one selected zone player. The method further includes receiving a command to change at least one of a respective volume of one or more of the at least one selected zone player or the group volume, and transmitting an indication of the received command to one or more of the at least one selected zone player.

Abstract: Techniques described herein enable wireless payment reader to transition between lower-power and higher-power states while still performing cryptographic operations for securing payment data without undue latency caused by the transition between sleep and awake power states. For instance, a wireless payment reader may store information associated with cryptographic operations performed by the wireless payment reader in persistent memory of the wireless payment reader so that this information may be retained when the wireless payment reader enters a low-power, sleep state. Thus, when the wireless payment reader awakens from the low-power state, the wireless payment reader may read the cryptographic information from the local persistent memory rather than needing to request this information from a payment service.

Abstract: Embodiments described herein provide a technique to crowdsource labeling of training data for a machine learning model while maintaining the privacy of the data provided by crowdsourcing participants. Client devices can be used to generate proposed labels for a unit of data to be used in a training dataset. One or more privacy mechanisms are used to protect user data when transmitting the data to a server. The server can aggregate the proposed labels and use the most frequently proposed labels for an element as the label for the element when generating training data for the machine learning model. The machine learning model is then trained using the crowdsourced labels to improve the accuracy of the model.

Abstract: This disclosure provides methods, devices and systems for protecting latency-sensitive communications during restricted target wake time (r-TWT) service periods (SPs). Some implementations more specifically relate to coordinated scheduling of r-TWT SPs between OBSSs. In some aspects, a first AP may coordinate with a second AP in scheduling r-TWT SPs so that latency-sensitive traffic in a first BSS does not interfere or collide with latency-sensitive traffic in a second BSS overlapping the first BSS. In some implementations, the first and second APs may schedule their respective r-TWT SPs to be orthogonal in time. In some other implementations, the first and second APs may schedule their r-TWT SPs to overlap in time, while allocating coordinated resources to concurrent or overlapping latency-sensitive traffic in the first and second BSSs (such as in accordance with one or more multi-AP coordination techniques).

Abstract: Systems and methods are disclosed for detecting and predicting the motion of objects within the surrounding environment of a system such as an autonomous vehicle. For example, an autonomous vehicle can obtain sensor data from a plurality of sensors comprising at least two different sensor modalities (e.g., RADAR, LIDAR, camera) and fused together to create a fused sensor sample. The fused sensor sample can then be provided as input to a machine learning model (e.g., a machine learning model for object detection and/or motion prediction). The machine learning model can have been trained by independently applying sensor dropout to the at least two different sensor modalities. Outputs received from the machine learning model in response to receipt of the fused sensor samples are characterized by improved generalization performance over multiple sensor modalities, thus yielding improved performance in detecting objects and predicting their future locations, as well as improved navigation performance.

Abstract: Apparatuses, methods, and systems comprising reconfigurable motorized conveyor rollers are provided. The example reconfigurable motorized conveyor roller includes a housing with a first end and a second end opposite to the first end. The housing includes a plurality of curved plates that at least partially form a cylindrical tube. The reconfigurable motorized conveyor roller includes a motor assembly and a drive assembly at least partially disposed within the housing that are configured to cause rotation of at least a portion of the reconfigurable motorized conveyor roller. And, the reconfigurable motorized conveyor roller includes a housing adjustment assembly disposed within the housing that is operable to modify one or more dimensions of the housing.

Abstract: In general, various aspects provide methods, apparatuses, systems, computing devices, computing entities, and/or the like for performing data discovery on a target computing system. In various aspects, a third party computing connects, via a public data network, to an edge node of the target computing system and instructs the target computing system to execute jobs to discover target data stored in data repositories in a private data network in the target computing system. In some aspects, the third party computing system may schedule the jobs on the target computing system based on computing resource availability on the target computing system.

Abstract: A method performed by a cloud system includes, subsequent to the cloud system connecting to one of a cloud provider and a Software-as-a-Service (SaaS) application, scanning data stored therein for one or more users associated with a tenant of a plurality of tenants of the cloud system; detecting an incident in the data during the scanning; maintaining details of the incident in an in-memory data store; and providing a notification to the tenant of the incident.

Abstract: Systems and methods for managing asynchronous resets in an SoC have been described. In an illustrative, non-limiting embodiment, a reset generation circuit in an SoC, may include a first reset generation circuit configured to enable a first reset signal based, at least in part, upon a clock signal and an indication to reset. The reset generation circuit may also include a second reset generation circuit coupled to the first reset generation circuit, in which the second reset generation circuit is configured to enable a second reset signal after the first reset signal is enabled. The first reset signal and the second reset signal are both provided to a component of the SoC.

Abstract: A computer implemented method is provided. A number of processor units identify a number of candidate applications for processing requests based on types of application programming interface for each application. The number of processor units validate metadata related to status of applications for each application in the number of candidate applications. The number of processor units select a subgroup of applications from the number of candidate applications to process requests based on the validated metadata.

Abstract: An IC device may include a CMOS layer and memory layers at the frontside and backside of the CMOS layer. The CMOS layer may include one or more logic circuits, which may include MOSFET transistors. A memory layer may include one or more memory arrays. A memory array may include memory cells (e.g., DRAM cells), bit lines, and word lines. The logic circuits may include word line drivers and sense amplifiers. Word lines in different memory layers may share the same word line driver. Bit lines in different memory layers may share the same sense amplifier. The IC device may include front-back word line drivers, near-far sense amplifiers, near-far word line drivers, or front-back sense amplifiers. A memory layer may be bonded with the CMOS layer through a bonding layer that provides a bonding interface between the memory layer and the CMOS layer.