Patents by Inventor Abhishek

Abhishek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12266076
    Abstract: The present disclosure relates to systems, methods, and non-transitory computer-readable media that generates a design representation to further construct a digital design multigraph and generate a structural representation for a digital design document from the digital design multigraph. For instance, the disclosed systems generate a design representation of a digital design document that includes design properties with multiple digital design elements. In particular, the disclosed systems construct a digital design (multi-)graph from the design representation by generating nodes to represent digital design elements and edges based on relationships between these elements. In addition, the disclosed systems generate a structural representation based on the digital design multigraph for downstream applications.
    Type: Grant
    Filed: June 2, 2023
    Date of Patent: April 1, 2025
    Assignee: Adobe Inc.
    Inventors: David Bourgin, Peter O'Donovan, Oliver Brdiczka, Gregory St. Pierre, Abhishek Gulati
  • Patent number: 12267009
    Abstract: An air conditioning device includes a buck converter which comprises a switching device, an inductor, a diode and at least one capacitor. The diode is a SiC diode, and the buck converter further includes an attenuator associated to the SiC diode and a ferrite bead associated to the switching device.
    Type: Grant
    Filed: September 30, 2022
    Date of Patent: April 1, 2025
    Assignee: Copeland Europe GmbH
    Inventors: Kurt Jansen, Alex Popa, Izsak Kantor, Abhishek Deshpande
  • Patent number: 12267709
    Abstract: Methods, systems, and devices for wireless communications are described. In some aspects, two devices may support signaling and messaging designs that support bandwidths that are greater than 160 MHz for ranging null data packets (NDPs). For example, various signaling and messaging designs may support a use of a 320 MHz bandwidth for ranging NDPs as part of a ranging measurement procedure, which may offer greater resolution than narrower bandwidths. The signaling and messaging designs may include one or more updates for a null data packet announcement (NDPA) frame, for a trigger frame, for session negation messages (such as one or both of an initial fine timing measurement (IFTM) frame and an IFTM request (IFTMR) frame), for segmentation techniques for ranging NDPs, or for any combination thereof.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: April 1, 2025
    Assignee: QUALCOMM Incorporated
    Inventors: Yanjun Sun, Alireza Raissinia, Stephen Jay Shellhammer, Xiaoxin Zhang, George Cherian, Alfred Asterjadhi, Abhishek Pramod Patil
  • Patent number: 12265828
    Abstract: Methods, systems and computer program products are provided for automated runtime configuration for dataflows to automatically select or adapt a runtime environment or resources to a dataflow plan prior to execution. Metadata generated for dataflows indicates dataflow information, such as numbers and types of sources, sinks and operations, and the amount of data being consumed, processed and written. Weighted dataflow plans are created from unweighted dataflow plans based on metadata. Weights that indicate operation complexity or resource consumption are generated for data operations. A runtime environment or resources to execute a dataflow plan is/are selected based on the weighted dataflow and/or a maximum flow. Preferences may be provided to influence weighting and runtime selections.
    Type: Grant
    Filed: January 26, 2023
    Date of Patent: April 1, 2025
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Abhishek Uday Kumar Shah, Anudeep Sharma, Mark A. Kromer, Jikai Ma
  • Patent number: 12267364
    Abstract: A software-defined wide area network (SD-WAN) environment that leverages network virtualization management deployment is provided. Edge security services managed by the network virtualization management deployment are made available in the SD-WAN environment. Cloud gateways forward SD-WAN traffic to managed service nodes to apply security services. Network traffic is encapsulated with corresponding metadata to ensure that services can be performed according to the desired policy. Point-to-point tunnels are established between cloud gateways and the managed service nodes to transport the metadata to the managed service nodes using an overlay logical network. Virtual network identifiers (VNIs) in the metadata are used by the managed service nodes to identify tenants/policies.
    Type: Grant
    Filed: July 24, 2021
    Date of Patent: April 1, 2025
    Assignee: VMWare LLC
    Inventors: Pierluigi Rolando, Jayant Jain, Raju Koganty, Shadab Shah, Abhishek Goliya, Chandran Anjur Narasimhan, Gurudutt Maiya Belur, Vikas Kamath
  • Patent number: 12267211
    Abstract: In various embodiments, a process for determining metrics including resource expenditures of a digital service includes discovering a plurality of configuration items of a computing infrastructure. The process includes identifying a subset of the plurality of configuration items utilized to provide a digital service, obtaining a plurality of resource expenditures respectively associated with at least a portion of the plurality of configuration items, and associating a subset of the plurality of resource expenditures with the subset of the plurality of configuration items. The process includes aggregating the subset of the plurality of resource expenditures to generate a metric of the digital service.
    Type: Grant
    Filed: June 15, 2023
    Date of Patent: April 1, 2025
    Assignee: ServiceNow, Inc.
    Inventors: Abhishek Kumar, Aakash Umeshbhai Bhagat, Atul Gupta, Ramkumar Devanathan, Shruti Jain
  • Publication number: 20250103229
    Abstract: Examples disclosed herein include writing pages of data to blocks, the data associated with an operator; writing the blocks to a file based on a sequential arrangement of the data in the blocks; writing the file to a spill data store; and executing an instruction by programmable circuitry to batch read the blocks in sequential order from the spill data store to a local memory
    Type: Application
    Filed: February 8, 2024
    Publication date: March 27, 2025
    Inventors: Yida Wu, Abhishek Rawat, Vincent Kulandaisamy
  • Publication number: 20250103430
    Abstract: Apparatuses including a graphics processing unit, graphics multiprocessor, or graphics processor having an error detection correction logic for cache memory or shared memory are disclosed. In one embodiment, a graphics multiprocessor includes cache or local memory for storing data and error detection correction circuitry integrated with or coupled to the cache or local memory. The error detection correction circuitry is configured to perform a tag read for data of the cache or local memory to check error detection correction information.
    Type: Application
    Filed: October 4, 2024
    Publication date: March 27, 2025
    Applicant: Intel Corporation
    Inventors: Vasanth Ranganathan, Joydeep Ray, Abhishek R. Appu, Nikos Kaburlasos, Lidong Xu, Subramaniam Maiyuran, Altug Koker, Naveen Matam, James Holland, Brent Insko, Sanjeev Jahagirdar, Scott Janus, Durgaprasad Bilagi, Xinmin Tian
  • Publication number: 20250106110
    Abstract: A network function virtualization (NFV) orchestration service includes a centralized orchestration device and a multi-cluster container management (MCCM) platform. The centralized orchestration device stores a catalog of virtual network function descriptors (VNFDs) in an input language; generates, based on the catalog of VNFDs, intents for containerized network function (CNF) services; and stores the generated intents as blocks in a central intent database, wherein the blocks include an input data model for the CNF services. The MCCM platform includes one or more processors to receive and store a copy of the intent database; read design time policies from the copy of the intent database; and convert the input data model into a vendor-specific output data model in an output language.
    Type: Application
    Filed: December 10, 2024
    Publication date: March 27, 2025
    Inventors: Abhishek Kumar, Bharath Thiruveedula, Myron Eugene Bagwell, Hans Raj Nahata
  • Publication number: 20250103343
    Abstract: Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive data dependencies for one or more tasks comprising one or more producer tasks executing on the first processing resource and one or more consumer tasks executing on the second processing resource and move a data output from one or more producer tasks executing on the first processing resource to a cache memory communicatively coupled to the second processing resource. Other embodiments may be described and claimed.
    Type: Application
    Filed: November 21, 2024
    Publication date: March 27, 2025
    Applicant: INTEL CORPORATION
    Inventors: Christopher J. HUGHES, Prasoonkumar SURTI, Guei-Yuan LUEH, Adam T. LAKE, Jill BOYCE, Subramaniam MAIYURAN, Lidong XU, James M. HOLLAND, Vasanth RANGANATHAN, Nikos KABURLASOS, Altug KOKER, Abhishek R. Appu
  • Publication number: 20250107107
    Abstract: An IC device may include memory layers over a logic layer. A memory layer may include memory arrays and one or more peripheral circuits coupled to the memory arrays. A memory array may include memory cells arranged in rows and columns. A row of memory cells may be associated with a word line. A column of memory cells may be associated with a bit line. The logic layer includes one or more logic circuits that can control data read operations and data write operations of the memory layers. The logic layer may also include a power interconnect, which facilitates power delivery to the memory layers, and a signal interconnect, which facilitates signal transmission within the IC device. The IC device may further include vias that couple the memory layers to the logic layer. Each via may be connected to one or more memory layers and the logic layer.
    Type: Application
    Filed: September 21, 2023
    Publication date: March 27, 2025
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Sagar Suthram, Wilfred Gomes, Pushkar Sharad Ranade, Anand S. Murthy, Tahir Ghani
  • Publication number: 20250103547
    Abstract: Embodiments described herein include software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. One embodiment provides techniques to optimize training and inference on a systolic array when using sparse data. One embodiment provides techniques to use decompression information when performing sparse compute operations. One embodiment enables the disaggregation of special function compute arrays via a shared reg file. One embodiment enables packed data compress and expand operations on a GPGPU. One embodiment provides techniques to exploit block sparsity within the cache hierarchy of a GPGPU.
    Type: Application
    Filed: October 4, 2024
    Publication date: March 27, 2025
    Applicant: INTEL CORPORATION
    Inventors: Prasoonkumar Surti, Subramaniam Maiyuran, Valentin Andrei, Abhishek Appu, Varghese George, Altug Koker, Mike Macpherson, Elmoustapha Ould-Ahmed-Vall, Vasanth Ranganathan, Joydeep Ray, Lakshminarayanan Striramassarma, SungYe Kim
  • Publication number: 20250107108
    Abstract: An IC device may include memory layers bonded to a logic layer with inclination. An angle between a memory layer and the logic layer may be in a range from approximately 0 to approximately 90 degrees. The memory layers may be over the logic layer. The IC device may include one or more additional logic layers that are parallel to a memory layer or perpendicular to a memory layer. The one or more additional logic layers may be over the logic layer. A memory layer may include memory cells. The logic layer may include logic circuits (e.g., sense amplifier, word line driver, etc.) that control the memory cells. Bit lines (or word lines) in different memory layers may be coupled to each other. A bit line and a word line in a memory layer may be controlled by logic circuits in different logic layers.
    Type: Application
    Filed: September 25, 2023
    Publication date: March 27, 2025
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Sagar Suthram, Wilfred Gomes, Tahir Ghani, Anand S. Murthy, Pushkar Sharad Ranade
  • Publication number: 20250106129
    Abstract: Systems, methods, and computer-readable media for managing compromised sensors in multi-tiered virtualized environments. In some embodiments, a system can receive, from a first capturing agent deployed in a virtualization layer of a first device, data reports generated based on traffic captured by the first capturing agent. The system can also receive, from a second capturing agent deployed in a hardware layer of a second device, data reports generated based on traffic captured by the second capturing agent. Based on the data reports, the system can determine characteristics of the traffic captured by the first capturing agent and the second capturing agent. The system can then compare the characteristics to determine a multi-layer difference in traffic characteristics. Based on the multi-layer difference in traffic characteristics, the system can determine that the first capturing agent or the second capturing agent is in a faulty state.
    Type: Application
    Filed: December 6, 2024
    Publication date: March 27, 2025
    Inventors: Navindra Yadav, Abhishek Ranjan Singh, Anubhav Gupta, Shashidhar Gandham, Jackson Ngoc Ki Pang, Shih-Chun Chang, Hai Trong Vu
  • Publication number: 20250106141
    Abstract: Some embodiments provide a method for controlling flow processing by an edge cluster including a first edge machine set operating in a first location set of a public cloud and a second edge machine set operating in a second location set of the public cloud. A controller set configures first and second managed forwarding element (MFE) sets operating in the first and second location sets respectively, with first and second forwarding rule sets to respectively forward first and second flows sets to the first and second edge machine sets for performing services. The first forwarding rule set specifies a first network address set for the first edge machine set, and the second forwarding rule set specifies a second network address set for the second edge machine set. The controller set monitors each edge machine to determine whether it is available to perform the services.
    Type: Application
    Filed: April 26, 2024
    Publication date: March 27, 2025
    Inventors: Minjal Agarwal, Yong Wang, Abhishek Goliya, Kai-Wei Fan
  • Publication number: 20250099015
    Abstract: A brain control interface system for determining a baseline for detecting brain activity of a user is disclosed. The brain control interface system comprising: a brain control interface configured to detect brain signals indicative of brain activity of a user in an environment, a memory configured to store activities of the user associated with different light scenes, a processor configured to: select, from the activities stored in the memory, a first activity of the user, control one or more lighting devices according to a first light scene associated with the first activity, detect brain signals of the user while the first light scene is active, determine, based on the detected brain signals, a first baseline for the brain signals, and store an association between the first baseline and the first light scene and/or the first activity.
    Type: Application
    Filed: January 13, 2023
    Publication date: March 27, 2025
    Inventors: ABHISHEK MURTHY, DAKSHA YADAV, PETER DEIXLER
  • Publication number: 20250104760
    Abstract: An IC device may include memory layers over a logic layer. A memory layer includes memory arrays, each of which includes memory cells arranged in rows and columns. A row of memory cells may be associated with a word line. A column of memory cells may be associated with a bit line. Bit lines of different memory arrays may be coupled using one or more vias or source/drain electrodes of transistors in the memory arrays. Alternatively, word lines of different memory arrays may be coupled using one or more vias or gate electrodes of transistors in the memory arrays. The logic layer has a logic circuit that can control data read operations and data write operations of the memory layers. The logic layer may include a power interconnect, which facilitates power delivery to the memory layers, and a signal interconnect, which facilitates signal transmission within the memory device.
    Type: Application
    Filed: September 21, 2023
    Publication date: March 27, 2025
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Sagar Suthram, Wilfred Gomes, Anand S. Murthy, Tahir Ghani, Pushkar Sharad Ranade
  • Publication number: 20250103546
    Abstract: Embodiments are generally directed to cache structure and utilization. An embodiment of an apparatus includes one or more processors including a graphics processor; a memory for storage of data for processing by the one or more processors; and a cache to cache data from the memory; wherein the apparatus is to provide for dynamic overfetching of cache lines for the cache, including receiving a read request and accessing the cache for the requested data, and upon a miss in the cache, overfetching data from memory or a higher level cache in addition to fetching the requested data, wherein the overfetching of data is based at least in part on a current overfetch boundary, and provides for data is to be prefetched extending to the current overfetch boundary.
    Type: Application
    Filed: October 4, 2024
    Publication date: March 27, 2025
    Applicant: Intel Corporation
    Inventors: Altug Koker, Lakshminarayanan Striramassarma, Aravindh Anantaraman, Valentin Andrei, Abhishek R. Appu, Sean Coleman, Varghese George, Pattabhiraman K, Mike MacPherson, Subramaniam Maiyuran, ElMoustapha Ould-Ahmed-Vall, Vasanth Ranganathan, Joydeep Ray, Jayakrishna P S, Prasoonkumar Surti
  • Publication number: 20250103894
    Abstract: Retrieving content items in response to a query in a way that increases user satisfaction and increases chances of users consuming a retrieved content item is not trivial. One retrieval strategy may include dividing the content items into buckets according to a dimension about the content items and retrieving a top K number of items from different buckets to balance semantic affinity and the dimension. Choosing an optimal K for different buckets for a given query can be a challenge. Reinforcement learning can be used to train and implement an agent model that can choose the optimal K for different buckets.
    Type: Application
    Filed: January 26, 2024
    Publication date: March 27, 2025
    Applicant: Roku, Inc.
    Inventors: Abhishek Majumdar, Yuxi Liu, Kapil Kumar, Nitish Aggarwal, Manasi Deshmukh, Danish Nasir Shaikh, Ravi Tiwari
  • Publication number: 20250103030
    Abstract: A system and method for monitoring and controlling an industrial process using a data model extensible to different industry applications. The system is configured to: receive data describing the industrial process from one or more data sources in a first format; contextualize and transform the data by determining one or more tags for the data, the one or more tags comprising context information describing characteristics of the entities involved in the industrial process; generate a data model describing the industrial process based on the one or more tags; receive a first indication from a user indicating a first industry application to which the data model will be applied; and extend the data model to include a second plurality of nodes representing entities associated with the first industry application and a second plurality of edges connecting the second plurality of nodes and describing relationships between the second plurality of nodes.
    Type: Application
    Filed: September 27, 2023
    Publication date: March 27, 2025
    Applicant: ROCKWELL AUTOMATION TECHNOLOGIES, INC.
    Inventors: Abhishek Negi, Douglas D. Fisher, Jennifer M. Kite, Ajai Singh