Abstract: A device and fabrication techniques are described that employ wafer-level packaging techniques for fabricating semiconductor devices that include a pad defined contact. In implementations, the wafer-level package device that employs the techniques of the present disclosure includes a substrate, a passivation layer, a top metal contact pad, a thin film with a via formed therein, a redistribution layer structure configured to contact the top metal contact pad, and a dielectric layer on the thin film and the redistribution layer structure. In implementations, a process for fabricating the wafer-level package device that employs the techniques of the present disclosure includes processing a substrate, forming a passivation layer, depositing a top metal contact pad, forming a thin film with a via formed therein, forming a redistribution layer structure in the via formed in the thin film, and forming a dielectric layer on the thin film and the redistribution layer structure.

Abstract: Systems, apparatuses and methods may provide for technology that determines a position associated with one or more polygons in unresolved surface data and select an anti-aliasing sample rate based on a state of the one or more polygons with respect to the position. Additionally, the unresolved surface data may be resolved at the position in accordance with the selected anti-aliasing sample rate, wherein the selected anti-aliasing sample rate varies across a plurality of pixels. The position may be a bounding box, a display screen coordinate, and so forth.

Abstract: A system may include a processor and a memory, the processor having at least one cache as well as memory access monitoring logic. The cache may include a plurality of sets, each set having a plurality of cache lines. Each cache line includes several bits for storing information. During normal operation, the memory access monitoring logic may monitor for a memory access pattern indicative of a side-channel attack (e.g., an abnormally large number of recent CLFLUSH instructions). Upon detecting a possible side-channel attack, the memory access monitoring logic may implement one of several mitigation policies, such as, for example, restricting execution of CLFLUSH operations. Due to the nature of cache-timing side-channel attacks, this prevention of CLFLUSH may prevent attackers utilizing such attacks from gleaning meaningful information.

Abstract: A system for building, training and productionizing machine learning models is disclosed. A model training specification is received, and a plurality of sets of hyper-parameters is obtained. Sets of training data and hyper parameter sets are distributed to distributed training systems. Models are trained in parallel using different sets of training data. Models are trained using multiple sets of hyper parameters. A candidate hyper-parameter set is selected, based on a measure of estimated effectiveness of the trained predictive models, and a production predictive model is generated by training a predictive model using the selected candidate hyper-parameter set and the complete set of training data.

Abstract: There is disclosed in one example a computing apparatus, including: a cache; a caching agent (CA); an integrated input/output (IIO) block to provide a cache coherent interface to a peripheral device at a first speed; a core configured to poll an address within the cache via the CA, wherein the address is to receive incoming data from the peripheral device via the IIO, and wherein the core is capable of polling the address at a second speed substantially greater than the first speed; and a hardware uncore agent configured to: identify a collision between the core and the IIO including determining that the core is polling the address at a rate that is determined to interfere with access to the address by the IIO; and throttle the core's access to the address.

Abstract: A memory circuit has compute-in-memory (CIM) circuitry that performs computations based on time-to-digital conversion (TDC). The memory circuit includes an array of memory cells addressable with column address and row address. The memory circuit includes CIM sense circuitry to sense a voltage for multiple memory cells triggered together. The CIM sense circuitry including a TDC circuit to convert a time for discharge of the multiple memory cells to a digital value. A processing circuit determines a value of the multiple memory cells based on the digital value.

Abstract: Techniques and mechanisms for a memory device to perform in-memory computing based on a logic state which is detected with a voltage-controlled oscillator (VCO). In an embodiment, a VCO circuit of the memory device receives from a memory array a first signal indicating a logic state that is based on one or more currently stored data bits. The VCO provides a conversion from the logic state being indicated by a voltage characteristic of the first signal to the logic state being indicated by a corresponding frequency characteristic of a cyclical signal. Based on the frequency characteristic, the logic state is identified and communicated for use in an in-memory computation at the memory device. In another embodiment, a result of the in-memory computation is written back to the memory array.

Abstract: The present disclosure includes systems and methods for securing data direct I/O (DDIO) for a secure accelerator interface, in accordance with various embodiments. Historically, DDIO has enabled performance advantages that have outweighed its security risks. DDIO circuitry may be configured to secure DDIO data by using encryption circuitry that is manufactured for use in communications with main memory along the direct memory access (DMA) path. DDIO circuitry may be configured to secure DDIO data by using DDIO encryption circuitry manufactured for use by or manufactured within the DDIO circuitry. Enabling encryption and decryption in the DDIO path by the DDIO circuitry has the potential to close a security gap in modern data central processor units (CPUs).

Abstract: Techniques for providing an uninterruptible power supply are disclosed. An example system includes three single-phase Uninterruptible Power Supplies (UPSs) and an adapter. The adapter is to receive three-phase AC power, and separate the three-phase AC power into three separate single-phase outputs. Each single-phase output is coupled to an input of one of the three single-phase UPSs. An output of each one of the single-phase UPSs is coupled to one of three single-phase inputs of the adapter, and the adapter is to combine the three single-phase inputs into a single three-phase output.

Abstract: A system and a method for detecting fraudulent transactions at a transaction site by analyzing pattern of events associated with one or more transactions are provided. The present invention provides for forming a collection of most probable fraudulent patterns and true patterns associated with one or more transactions, selecting a pattern classification technique, generating a data input from an ongoing transaction that is interpretable by the selected pattern classification technique, and effectively and efficiently categorising ongoing transaction into fraudulent and genuine transactions using selected pattern classification technique. The present invention may be utilized in a variety of applications where discrete time-ordered visual events are associated with a transaction, for example: vehicles detected in relation to a transit point, badge or card swipes from an automated door lock etc., which indicate trespassing, theft and unauthorized access to restricted areas etc.

Abstract: A memory circuit has compute-in-memory circuitry that enables a multiply-accumulate (MAC) operation based on shared charge. Row access circuitry drives multiple rows of a memory array to multiply a first data word with a second data word stored in the memory array. The row access circuitry drives the multiple rows based on the bit pattern of the first data word. Column access circuitry drives a column of the memory array when the rows are driven. Accessed rows discharge the column line in an accumulative fashion. Sensing circuitry can sense voltage on the column line. A processor in the memory circuit computes a MAC value based on the voltage sensed on the column.

Abstract: An apparatus is described. The apparatus includes a compute in memory circuit. The compute in memory circuit includes a memory circuit and an encoder. The memory circuit is to provide 2m voltage levels on a read data line where m is greater than 1. The memory circuit includes storage cells sufficient to store a number of bits n where n is greater than m. The encoder is to receive an m bit input and convert the m bit input into an n bit word that is to be stored in the memory circuit, where, the m bit to n bit encoding performed by the encoder creates greater separation between those of the voltage levels that demonstrate wider voltage distributions on the read data line than others of the voltage levels.

Abstract: A platform for storing and reporting of data records associated with management of a population of managed devices is disclosed. Data records are injected into a hosted computing environment in which data processing services are arranged to store and generate analytics associated with a mobile device management (MDM) platform.

Abstract: A system and method including, for each component of a system, defining filter flags that identify measurements that correspond to a particular operating condition of the respective component, the identified measurements being sensor measurements relevant to build a predictive model of expected output for each component of the system; defining input sensors for each of the components; defining at least one output sensor for each of the components; filtering data from the system based on the defined filter flags for each respective component; building, based on the defined input sensors for each respective component, a predictive model for the defined output sensor; determining a divergence between actual data values and expected values predicted by the model for each respective component; determining a component-specific anomaly score for each component of the system; and storing a record of the component-specific anomaly score for each component of the system.

Abstract: Certain aspects of the present disclosure provide methods and apparatus relating to distribution networks that utilize point-to-point communication between devices. The method comprises generating a frame with information indicating in which time division duplex (TDD) time slots, in a service period (SP) within a data transfer interval (DTI) of the frame, another apparatus is allowed to communicate.

Abstract: A semiconductor chip is described. The semiconductor chip includes a compute-in-memory (CIM) circuit to implement a neural network in hardware. The semiconductor chip also includes at least one output that presents samples of voltages generated at a node of the CIM circuit in response to a range of neural network input values applied to the CIM circuit to optimize the CIM circuit for the neural network.

Abstract: A system may include a processor and a memory, the processor having at least one cache. The cache may include a plurality of sets, each set having a plurality of cache lines. Each cache line may include several bits for storing information, including at least a “shared” bit to indicate whether the cache line is shared between different processes being executed by the processor. The example cache may also include shared cache line detection and eviction logic. During normal operation, the cache logic may monitor for a context switch (i.e., determine if the processor is switching from executing instructions for a first process to executing instructions for a second process). Upon a context switch, the cache logic may evict the shared cache lines (e.g., the cache lines with a shared bit of 1). Due to the nature of cache-timing side-channel attacks, this eviction of shared cache lines may prevent attackers utilizing such attacks from gleaning meaningful information.

Abstract: The systems and methods described herein can be applied to a vehicle equipped with a sensor suite that can observe information about a user, for example, a driver or passenger, within a vehicle. The system can determine a action being conducted by a user or an event associated with the user. Then, the navigation system can augment or learn what type of route or conditions allows the user to conduct the action or event. From the learned information, the navigation system can determine a route that best assists with the action or event regardless of whether the route is the shortest or quickest. As such, the vehicle tailors the chosen navigation route based on the user's conditions or circumstances rather than the driving environment.

Abstract: Examples include an apparatus which accesses secure pages in a trust domain using secure lookups in first and second sets of page tables. For example, one embodiment of the processor comprises: a decoder to decode a plurality of instructions including instructions related to a trusted domain; execution circuitry to execute a first one or more of the instructions to establish a first trusted domain using a first trusted domain key, the trusted domain key to be used to encrypt memory pages within the first trusted domain; and the execution circuitry to execute a second one or more of the instructions to associate a first process address space identifier (PASID) with the first trusted domain, the first PASID to uniquely identify a first execution context associated with the first trusted domain.

Abstract: Compute-in memory circuits and techniques are described. In one example, a memory device includes an array of memory cells, the array including multiple sub-arrays. Each of the sub-arrays receives a different voltage. The memory device also includes capacitors coupled with conductive access lines of each of the multiple sub-arrays and circuitry coupled with the capacitors, to share charge between the capacitors in response to a signal. In one example, computing device, such as a machine learning accelerator, includes a first memory array and a second memory array. The computing device also includes an analog processor circuit coupled with the first and second memory arrays to receive first analog input voltages from the first memory array and second analog input voltages from the second memory array and perform one or more operations on the first and second analog input voltages, and output an analog output voltage.