Abstract: Embodiments relate generally to systems and methods for communicating data from a flame detector. A method may comprise detecting, by the flame detector, data related to a fire event; communicating, by the flame detector, the fire event data to a wireless device; forwarding, by the wireless device, the fire event data to a cloud database; accessing the fire event data, via the cloud database, by a central server controlled by an operator of the flame detector; analyzing, by the central server, the fire event data; automatically generating a report based on the analysis of the fire event data, by the central server; and communicating the generated report to a customer employing the flame detector.

Abstract: Rotatable cutting element assemblies includes a sleeve, a centering element positioned at least partially within the sleeve, a biasing element configured to apply a force against the centering element, and a rotatable cutting element coupled to the centering element and configured to rotate relative to the sleeve. Earth-boring tools include a tool body and at least one rotatable cutting element assembly coupled to the tool body. The at least one rotatable cutting element assembly includes a sleeve fixedly coupled to the tool body, a centering element positioned at least partially within the sleeve, a rotatable cutting element coupled to the centering element, and a biasing element configured to apply a force against the centering element. Methods of forming an earth-boring tool include positioning a centering element within a sleeve, fixedly coupling the sleeve to a tool body, and coupling a rotatable cutting element to the centering element.

Abstract: An earth-boring tool is comprised of a body, blade, and cutting element assembly. The sleeve of the cutting element assembly has an interior surface that defines a cavity. A rotatable cutting element fits within the cavity secured by a threaded end cap. The rotatable cutting element is comprised of a polycrystalline hard material bonded to a supporting substrate. The polycrystalline hard material has an end cutting surface on a first end and the supporting substrate has a back surface on a second end opposite the first end. An annular ring has an upper surface in contact with the back surface of the supporting substrate and a lower surface in contact with the upper surface of the end cap. There is a spring in a void defined by an inner surface of the annular ring, the back surface of the supporting substrate, and the upper surface of the end cap.

Abstract: An operating system of a computing device determines an importance of the threads running on the computing device, such as assigning the importance of the threads as critical or non-critical. The operating system determines when there are no threads having at least a threshold importance (e.g., no critical threads), and forces one or more components of the computing device into a forced idle state in response to determining that there are no threads having at least the threshold importance. The forced idle state of a device component is a low power state, such as a state in which program instructions are not executed, so the computing device is forced into a forced idle state that reduces power usage in the computing device despite there being threads (e.g., non-critical threads) to be executed.

Abstract: Devices and techniques are generally described for image editing. In various examples, color image data and segmentation image data may be identified. In some examples, the segmentation image data may identify a first portion of the color image data as a foreground region and a second portion of the color image data as a background region. A segmentation boundary may be identified between the foreground region and the background region. A first area of the second portion may be identified, where the first area extends from the segmentation boundary to a first area outer boundary. A second area of the second portion may be identified, where the second area extends from the first area outer boundary to a second area outer boundary. A blended and blurred representation of the first area and the second area may be generated.

Abstract: Methods for performing a structured collection procedure by utilizing a collection device are disclosed herein, in which a collection procedure is initiated for performing one or more data collections for one or more data event instances occurring according to a schedule of events. Each data event instances comprises a data collection pertaining to a biomarker to be performed according to one or more conditions of an adherence criterion. Each data event instance is determined to be successful or unsuccessful on the basis of actual performance of the data collection and meeting certain conditions of the predetermined adherence criteria for the data event instance. Contextual information for successful data collections is generated and a data file generated for storing records relating to successful data collections.

Abstract: In various embodiments, apparatuses for receiving and supporting one or more components during processing thereof at process temperatures greater than approximately 1000° C. feature refractory metal shelves separated by refractory metal support posts.

Abstract: A system includes at least one processor configured to identify multiple nodes coupled to at least one network of an industrial plant, obtain configuration data from each of the nodes, parse the configuration data to extract specified information from the configuration data, and store the extracted specified information in a specified format. To parse the configuration data for each node, the at least one processor may be configured to generate a memory layout for the configuration data from the node, open a checkpoint file containing the configuration data from the node, and identify at least one point and header information for the at least one point in the checkpoint file using the memory layout. To identify the multiple nodes, the at least one processor can be configured to generate a network diagram of the nodes coupled to the at least one network and identify the nodes from the network diagram.

Abstract: The present disclosure is directed to systems and methods of implementing a neural network using in-memory, bit-serial, mathematical operations performed by a pipelined SRAM architecture (bit-serial PISA) circuitry disposed in on-chip processor memory circuitry. The on-chip processor memory circuitry may include processor last level cache (LLC) circuitry. The bit-serial PISA circuitry is coupled to PISA memory circuitry via a relatively high-bandwidth connection to beneficially facilitate the storage and retrieval of layer weights by the bit-serial PISA circuitry during execution. Direct memory access (DMA) circuitry transfers the neural network model and input data from system memory to the bit-serial PISA memory and also transfers output data from the PISA memory circuitry to system memory circuitry.

Abstract: Techniques and mechanisms for configuring a memory device to perform a sequence of in-memory computations. In an embodiment, a memory device includes a memory array and circuitry, coupled thereto, to perform data computations based on the data stored at the memory array. Based on instructions received at the memory device, control circuitry is configured to enable an automatic performance of a sequence of operations. In another embodiment, the memory device is coupled in an in-series arrangement of other memory devices to provide a pipeline circuit architecture. The memory devices each function as a respective stage of the pipeline circuit architecture, where the stages each perform respective in-memory computations. Some or all such stages each provide a different respective layer of a neural network.

Abstract: Described herein are systems and methods for scheduling a resource that is shared by multiple people. The shared resource is included in a plurality of shared resources, and a number of attributes are associated with the plurality of shared resources. The attributes are grouped and arranged in a hierarchy. When a shared resource is to be used or scheduled, the hierarchy is analyzed to determine one or more shared resources in the plurality of shared resources to suggest to a requestor scheduling the shared resource.

Abstract: The present disclosure is directed to systems and methods of implementing an analog neural network using a pipelined SRAM architecture (“PISA”) circuitry disposed in on-chip processor memory circuitry. The on-chip processor memory circuitry may include processor last level cache (LLC) circuitry. One or more physical parameters, such as a stored charge or voltage, may be used to permit the generation of an in-memory analog output using a SRAM array. The generation of an in-memory analog output using only word-line and bit-line capabilities beneficially increases the computational density of the PISA circuit without increasing power requirements.

Abstract: A system and a method for detecting anomalous activities in a distributed and decentralised network is provided. Anonymous users transacting in the network are identified and one or more transactional attributes are retrieved to define characteristics of users and associated transactional behaviour with other users. Further, user-level statistics are evaluated based on transactional attributes. Datatype representative of transactional behavior of users with other users is generated using user-level statistics of identified users. Users with similar transactional behavior are classified based on generated transactional attributes. One or more anomaly detection techniques are implemented for identifying optimum classification of users into data clusters based on the change detected in the classification of users in data clusters. Anomalous users are identified from the optimum classification for efficiently and effectively detecting anomalous activities in the network.

Abstract: The present disclosure is directed to systems and methods of implementing a neural network using in-memory mathematical operations performed by pipelined SRAM architecture (PISA) circuitry disposed in on-chip processor memory circuitry. A high-level compiler may be provided to compile data representative of a multi-layer neural network model and one or more neural network data inputs from a first high-level programming language to an intermediate domain-specific language (DSL). A low-level compiler may be provided to compile the representative data from the intermediate DSL to multiple instruction sets in accordance with an instruction set architecture (ISA), such that each of the multiple instruction sets corresponds to a single respective layer of the multi-layer neural network model. Each of the multiple instruction sets may be assigned to a respective SRAM array of the PISA circuitry for in-memory execution.

Abstract: Various example embodiments herein disclose a flip-flop including a master latch comprising one of: a plurality of P-type metal-oxide-semiconductor (PMOS) and a plurality of N-type metal-oxide-semiconductor (NMOS). A slave latch includes one of: a plurality of PMOS and a plurality of NMOS. An inverted clock signal input is communicatively connected with the master latch and the slave latch. The master latch includes a single pre-charge node. The single pre-charge node sets up a data capture path in the flip flop. Data is stored in the master latch and the slave latch via the pre-charge node.

Abstract: A circuit includes a dummy wordline, a dummy bitline, and a dummy cell coupled to the dummy bitline. The dummy cell includes an active pulldown nMOSFET and a pass nMOSFET having a gate connected to the dummy wordline, a first source terminal connected to the drain terminal of the active pulldown nMOSFET, and a drain terminal connected to the dummy bitline. The circuit further includes a substrate-connected dummy bitline coupled to the source terminal of each active pulldown nMOSFET and coupled to a substrate.

Abstract: Techniques and mechanisms for performing in-memory computations with circuitry having a pipeline architecture. In an embodiment, various stages of a pipeline each include a respective input interface and a respective output interface, distinct from said input interface, to couple to different respective circuitry. These stages each further include a respective array of memory cells and circuitry to perform operations based on data stored by said array. A result of one such in-memory computation may be communicated from one pipeline stage to a respective next pipeline stage for use in further in-memory computations. Control circuitry, interconnect circuitry, configuration circuitry or other logic of the pipeline precludes operation of the pipeline as a monolithic, general-purpose memory device. In other embodiments, stages of the pipeline each provide a different respective layer of a neural network.

Abstract: The present disclosure is directed to systems and methods of bit-serial, in-memory, execution of at least an nth layer of a multi-layer neural network in a first on-chip processor memory circuitry portion contemporaneous with prefetching and storing layer weights associated with the (n+1)st layer of the multi-layer neural network in a second on-chip processor memory circuitry portion. The storage of layer weights in on-chip processor memory circuitry beneficially decreases the time required to transfer the layer weights upon execution of the (n+1)st layer of the multi-layer neural network by the first on-chip processor memory circuitry portion. In addition, the on-chip processor memory circuitry may include a third on-chip processor memory circuitry portion used to store intermediate and/or final input/output values associated with one or more layers included in the multi-layer neural network.

Abstract: A door includes a door frame, first and second door skins having rectangular outer peripheries and inner openings, and a frameless glazed unit received at the openings. The door skins include exterior surfaces facing away from the door frame and opposite interior surfaces facing and secured to opposite sides of the door frame. The exterior and interior surfaces of the first and second door skins establish integral lips and grooves of the first and second door skins Opposite sides of the frameless glazed unit directly contact and are sealed by the integral lips and sealant and/or adhesive contained in the grooves of the first and second door skins.

Abstract: In one or more implementations, a digital medium environment includes at least one computing device. Systems and techniques are described herein for inserting linked text fragments in a document layout of a document. By supporting multiple linked text fragments within a text frame, of both constant content and variable content, content of an asset is inserted into a text fragment while preserving the styling attributes of the text frame. Thus, manual efforts associated with reapplying styling attributes are avoided, unlike systems that do not distinguish between text fragments with constant content and text fragments with variable content within a text frame. Furthermore, a user interface is generated that exposes metadata of assets and a document layout. Content of an asset exposed via the user interface, once selected, is inserted into the document layout and exposed as a tagged text fragment, indicating the content is linked.