Abstract: A system and method include a server device which transmits a list of passengers for a vehicle route. The list of passengers may include profiles for each one of the passengers. The server device may further receive a unique identification for a passenger boarding a vehicle and compare the unique identification to the list of passengers for the vehicle route. The server device may further identify the passenger boarding the vehicle as being on board the vehicle in the profile for that passenger. The server device may further receive vehicle status information from the vehicle and transmit driver navigational information to a driver device. The server device may further transmit real time tracking data to a user device, including a map with an indicator of a current location of the vehicle.

Abstract: Disclosed herein are system, apparatus, article of manufacture, method and/or computer program product embodiments, and/or combinations and sub-combinations thereof, for determining a list of recommended items in response to a user query. An embodiment can generate an ordered relevance list of items, and determine an initial reward value based on an array of relevance scores and an array of revenue values corresponding to the ordered relevance list of items, a parameter alpha assigned to the array of relevance scores, and a parameter beta assigned to the array of revenue values. The embodiment can generate a next list of recommended items from an initial list of recommended items, and further calculate a next reward value associated with the next list of recommended items, and determine a list of recommended items in response to the query based on a comparison of the initial reward value and the next reward value.

Abstract: Embodiments herein relate to a multi-bit flip-flop circuit which uses unidirectional transistors to allow sharing of transistors among a set of flip-flops, while avoiding charge sharing within or between the flip-flops. Clock devices in the circuit can be shared to reduce the clock transistor gate capacitance and associated power consumption. The shared transistors can provide keeper circuits and/or tri-state inverters in a primary latch and a secondary latch in each flip-flop. One example implementation uses tri-state keeper sharing. Another example implementation uses tri-state keeper and/or pass gate sharing. Another example implementation uses pass gate sharing and no keeper.

Abstract: Provisioning of day-1 configuration templates is automated. Users are provided access to a Configuration Template User Interface (UI) for creating configuration templates. Input is received on the Configuration Template UI to create the configuration templates. A trigger is received by a configuration manager to initiate configuration of network devices or functions. The trigger includes one or more Template Identifiers (IDs) corresponding to the one or more configuration templates. Configuration files are generated based on the trigger and one or more Template IDs corresponding to the one or more configuration templates. Configuration files are sent from the configuration manager to the one or more network devices or functions to configure the one or more network devices or functions.

Abstract: A system and method for avoiding unintended acceleration is provided and includes a first integrated circuit-based electronic controller configured to receive acceleration and brake requests and provide a control output via a datalink dedicated to controlling a prime mover system of the vehicle, a three-axis accelerometer configured to provide acceleration outputs indicative of acceleration of the accelerometer relative to three dimensions, and a second integrated circuit-based electronic controller operative independently of the first integrated circuit-based controller configured to receive the acceleration and braking requests, receive the acceleration outputs of the three-axis accelerometer, and operatively coupled with the datalink. The second integrated circuit-based electronic controller is configured to determine an unintended acceleration event in response to the acceleration and braking requests, and the acceleration outputs of the three-axis accelerometer.

Abstract: The present disclosure describes systems and methods for detecting temperature in an electro-optical circuit (e.g., an electro-optical transceiver). According to an embodiment, an electro-optical circuit includes a photonic integrated circuit and an electronic integrated circuit. The photonic integrated circuit includes an optical component and a first resistor positioned by the optical component. The electronic integrated circuit determines a temperature for the optical component based on a first resistance of the first resistor.

Abstract: Techniques for facilitating voice based dictation of programming code within a context of an IDE are disclosed. Programming code is fed to a text-to-speech (TTS) model. The TTS model generates an audio file associated with the code. The audio file is then fed to a speech-to-text (STT) model. The STT model generates a transcription file associated with the audio file. Each respective line of code included in the programming code is mapped to a corresponding line of code included in the transcription file, resulting in generation of a list of phrase pairings. These phrase pairings represent relationships between actual code and how that actual code sounds if read out loud. An LLM then ingests the list of phrase pairings. The LLM identifies correlations between programming vocabulary that has specific meaning within the context of the IDE and how that programming vocabulary sounds if read out loud.

Abstract: Embodiments of the present disclosure provide method and apparatus for traffic probing. A method performed by a sender network function (NF) includes sending a first message to a receiver NF. The first message comprises a new HTTP header which comprises an NF instance identifier (ID) of the sender NF and an NF instance ID of the receiver NF.

Abstract: In some aspects, a program is executed on a coarse-grained reconfigurable (CGR) processor. The CGR determines that the program produces an output that includes a variable length tensor, determines a maximum size of the variable length tensor and sets, based on the maximum size, a maximum of a counter associated with the program. The counter is set to an initial value of zero. The CGR initiates execution of the program, causing the program to receive an input tensor. Based on determining that the program is operating on a first portion of the input tensor, the CGR performs an update to the counter, to create an updated counter, and communicates the updated counter to one or more consumers within the program. After determining that the program has completed operating on the input tensor, a final size of the output is communicated to one or more downstream consumers external to the program.

Abstract: A transistor may include a source region, a drain region, a channel region between the source region and the drain region in a first direction, a gate electrode, a source contact, and a drain contact. A first portion of the gate electrode is over the channel region in a second direction substantially perpendicular to the first direction. A second portion of the gate electrode is over a first portion of the drain region in the second direction. The source contact is over at least part of the source region. The drain contact is over a second portion of the drain region. A distance from an edge of the first portion of the drain region to an edge of the gate electrode or to an edge the first trench electrode in the first direction is greater than a fourth of a length of the gate electrode in the first direction.

Abstract: IC devices implementing memory with one access transistor coupled to multiple capacitors are disclosed. An example IC device includes a support structure (e.g., a substrate), an access transistor over the support structure, the access transistor having a region that is either a source region or a drain region, and a plurality of capacitors where at least two or more of the capacitors are in different layers above the access transistor. First capacitor electrodes of the plurality of capacitors are coupled to the region, and second capacitor electrodes of the plurality of capacitors are coupled to respective electrically conductive lines. IC devices implementing memory with one access transistor coupled to multiple capacitors as described herein may be used to address the scaling challenges of conventional 1T-1C memory technology and enable high-density embedded memory compatible with advanced CMOS processes.

Abstract: A patient positioning system includes a body, a pad, and a plurality of sensors. The body includes a first surface and a second surface. The first surface includes a high-friction material. The first surface is configured to adhere to a patient. The second surface includes a low-friction material. The pad is housed in the body. The pad is configured to deform in response to a pressure applied to the body. The sensors are housed in the body. The sensors are configured to sense the pressure applied to the body.

Abstract: An example IC device includes a support structure; a device layer over or at least partially in the support structure, the device layer comprising transistors; and an interconnect layer. The device layer is between the support structure and the interconnect layer, and the interconnect layer includes a first conductive line and a second conductive line stacked above the first conductive line. A first end of the first conductive line is substantially aligned with a first end of the second conductive line along a plane perpendicular to the substrate, and a second end of the first conductive line is closer to the plane than a second end of the second conductive line. Such an arrangement of conductive lines may be referred to as “flipped staircase.

Abstract: A system and method include a server device which identifies a plurality of stops for a vehicle among a fleet of vehicles. The server device also identifies stop locations for each one of the plurality of stops and a side of a street for each one of the plurality of stops. Once identified, the server devices generates an optimized route for service by the vehicle to service each one of the stop based on an optimized stop order for each one of the plurality of stops based on the stop locations being disposed only on the identified side of the street for each one of the plurality of stop locations. The optimized route may be provided to a driver device while the route and time of arrival information may be provided to a user.

Abstract: The present invention relates to long acting glucagon-like peptide-1 and human glucose- dependent insulinotropic polypeptide (GIP) agonist polypeptides which may be useful for treating type 2 diabetes mellitus (T2D), diabetes with obesity, obesity and hyperlipidemia.

Abstract: A method includes calibrating, at a wireless device, a wireless fidelity (Wi-Fi) chipset-level timer based on a time synchronization function (TSF) frame received from a Wi-Fi access point. The method also includes performing, at the wireless device, a coarse synchronization of a microcontroller-level or CPU-level timer based on the calibrated Wi-Fi chipset-level timer. The method further includes performing, at the wireless device, a fine synchronization of the microcontroller-level or CPU-level timer after the coarse synchronization. The fine synchronization is performed according to a first time scale measured in first time units and the coarse synchronization is performed according to a second time scale measured in second time units that are a multiple of the first time units.

Abstract: According to one example, the present disclosure involves a system including a data-communications server which uses client-specific sets of data that respectively indicate, for each of a plurality of disparate client entities, data services including data-communications call routing services and parked-call services to be provided on behalf of the client entity from among the client entities. The server is to access the client-specific sets of data (e.g., as may be stored in database of a memory circuit), and, in response, the server receives incoming calls involving user endpoint devices associated with respective ones of the client entities. These actions may be followed by the server providing the data services for the incoming calls in a manner consistent with the client-specific sets of data, and conveying for one of the incoming calls, one of multiple call-related context indications to one of the user endpoint devices.

Abstract: A User Plane Function (UPF) of 5G Core network performs a search for the next hop in the data path, using utilities (e.g., Internet Control Message Protocol (ICMP) trace route), and determines the capability of the next router and/or other hops in the path. The UPF updates (e.g., using the PATCH command) the Network Repository Function (NRF) with the gathered information. The UPF also updates the NRF the UPF's position in the current route, and the role(s) the UPF is playing at a given time, e.g., Branching Point (BP), Intermediate User Plane Function (I-UPF), and the like. The SMF is enabled to identify the UPF's capability for a given PDU Session. The selection of a given UPF for non-suitable roles can be prevented, and the UPF can be selected for those roles in which the UPF is more suitable at a given time.

Abstract: Disclosed herein are inhibitors, such as antibodies, and antigen-binding portions thereof, that selectively bind complexes of LTBP1-TGF? and/or LTBP3-TGF?. The application also provides methods of use of these inhibitors for, for example, inhibiting TGF? activation, and treating subjects suffering from TGF?-related disorders, such as fibrotic conditions. Methods of selecting a context-dependent or context-independent isoform-specific TGF? inhibitor for a subject in need thereof are also provided.

Abstract: There is provided an apparatus, method and medium. The apparatus comprises processing circuitry to process instructions and a reorder buffer identifying a plurality of entries having state information associated with execution of one or more of the instructions. The apparatus comprises allocation circuitry to allocate entries in the reorder buffer, and to allocate at least one compressed entry corresponding to a plurality of the instructions. The apparatus comprises memory access circuitry responsive to an address associated with a memory access instruction corresponding to access-sensitive memory and the memory access instruction corresponding to the compressed entry, to trigger a reallocation procedure comprising flushing the memory access instruction and triggering reallocation of the memory access instruction without the compression.