Abstract: A method encodes compositional data structures by receiving component sparse distributed representation arrays having a predetermined array length and target sparsity level, applying position-specific permutation transformations to encode ordinal position information, combining position-encoded arrays through bitwise union to generate an intermediate array, and processing the intermediate array through a dual-phase sparsity reduction procedure comprising a coarse additive phase and a fine subtractive phase controlled by a sparsity overshoot threshold to generate a composite encoded array. The dual-phase procedure converges in substantially constant iterations for 4 or more components with final sparsity tightly controlled around the target. A decoding method applies inverse position-specific transformations to generate position-decoded arrays, computes overlap scores with candidate components through bit counting operations, and determines component identities based on threshold comparison.

Abstract: A system, a method and a computer program product for protecting a speculative execution processor from side channel attacks, are disclosed. The system comprises a processing circuitry which performs an execution of a code segment, in one time period and copies, in another time period, only a committed portion of the executed code segment into a memory component which is accessible to read actions by an external processing unit. The speculative instructions are stored in an internal cache memory which is not accessible to read actions by the external processing unit.

Abstract: A system for training a quantized neural network dataset, comprising at least one hardware processor adapted to: receive input data comprising a plurality of training input value sets and a plurality of target value sets; in each of a plurality of training iterations: for each layer, comprising a plurality of weight values, of one or more of a plurality of layers of a neural network: compute a set of transformed values by applying to a plurality of layer values one or more emulated non-uniformly quantized transformations by adding to each of the plurality of layer values one or more uniformly distributed random noise values; and compute a plurality of output values; compute a plurality of training output values; and update one or more of the plurality of weight values to decrease a value of a loss function; and output the updated plurality of weight values of the plurality of layers.

Abstract: A system and method for protecting a speculative execution processor, from side channel attacks, are disclosed. The system comprises a processing circuitry, adapted to: in a first time period performing an execution of a code segment by storing speculative instructions in an internal cache memory which is inaccessible to read actions of an external processing unit; in a second time period copying only a committed portion of the executed code segment into another memory component which is accessible to read actions of the external processing unit. The first and second time periods are different and independent.

Abstract: A system for training a quantized neural network dataset, comprising at least one hardware processor adapted to: receive input data comprising a plurality of training input value sets and a plurality of target value sets; in each of a plurality of training iterations: for each layer, comprising a plurality of weight values, of one or more of a plurality of layers of a neural network: compute a set of transformed values by applying to a plurality of layer values one or more emulated non-uniformly quantized transformations by adding to each of the plurality of layer values one or more uniformly distributed random noise values; and compute a plurality of output values; compute a plurality of training output values; and update one or more of the plurality of weight values to decrease a value of a loss function; and output the updated plurality of weight values of the plurality of layers.

Abstract: A computerized method of creating a circuit logic model of a VLSI device, comprising mapping a plurality of logic function patterns of one or more circuits of a VLSI device through a plurality of probe iterations and generating a circuit logic model of the circuit(s) by reconstructing a logical function of a combinatorial logic of the circuit(s) based on analysis of the logic function patterns. Each of the probe iteration comprises switching between scan shift mode and functional mode of the VLSI device such that while the VLSI device operates in scan shift mode register(s) associated with the circuit(s) is accessed and while the VLSI device operates in functional mode external pin(s) of the VLSI device associated with the circuit(s) is probed and mapping a respective one of the logic function patterns according to a logic state of one or more bits in the register(s) and/or the external pin(s).

Abstract: A computerized method of creating a circuit logic model of a VLSI device, comprising mapping a plurality of logic function patterns of one or more circuits of a VLSI device through a plurality of probe iterations and generating a circuit logic model of the circuit(s) by reconstructing a logical function of a combinatorial logic of the circuit(s) based on analysis of the logic function patterns. Each of the probe iteration comprises switching between scan shift mode and functional mode of the VLSI device such that while the VLSI device operates in scan shift mode register(s) associated with the circuit(s) is accessed and while the VLSI device operates in functional mode external pin(s) of the VLSI device associated with the circuit(s) is probed and mapping a respective one of the logic function patterns according to a logic state of one or more bits in the register(s) and/or the external pin(s).

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract: Embodiments of the present invention provide a resource management mechanism to monitor the availability of resources, detect the cause of a rejection, distinguish between different types of rejections, and manage the different types accordingly. For example, a queue manager in accordance with embodiments of the invention may be able to classify rejected requests, for example, as either a “long reject” or a “short reject” based on the cause of the rejection and the amount of time the rejection conditions are expected to remain valid. A short reject request may be rescheduled in an appropriate service queue, while a long reject request may be suspended in a reject queue. Other features are described and claimed.

Abstract: Briefly, a system and a method to efficiently track changes in memory or storage areas, for example, in cache memories of computers and electronic systems. A method in accordance with an exemplary embodiment of the invention includes, for example, updating a tracking list with an address and/or a corresponding address to be updated of a changed entry in an intermediate memory. A system in accordance with an exemplary embodiment of the invention may include, for example, a tracking unit to track the locations of potential data discrepancies between a reference memory and an intermediate memory.

Abstract: A cache management logistics controls a transfer of a trace. A first cache couples to the cache management logistics to evict the trace based on a replacement mechanism. A second cache couples to the cache management logistics to receive the trace based on a number of accesses to the trace.

Abstract: In an embodiment, a method includes receiving a binary of a program code. The binary is based on a first instruction set architecture. The method also includes translating the binary, wherein the translated binary is based on a combination of the first instruction set architecture and a second instruction set architecture.

Abstract: Embodiments of the present invention provide a resource management mechanism to monitor the availability of resources, detect the cause of a rejection, distinguish between different types of rejections, and manage the different types accordingly. For example, a queue manager in accordance with embodiments of the invention may be able to classify rejected requests, for example, as either a “long reject” or a “short reject” based on the cause of the rejection and the amount of time the rejection conditions are expected to remain valid. A short reject request may be rescheduled in an appropriate service queue, while a long reject request may be suspended in a reject queue. Other features are described and claimed.