Patents by Inventor Abraham Mendelson
Abraham Mendelson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110161703Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.Type: ApplicationFiled: March 11, 2011Publication date: June 30, 2011Inventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David Harriman, Mark Rosenbluth, Ajay Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert Blankenship, Ohad Falik, Avi Abraham Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia
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Patent number: 7958510Abstract: Embodiments of the present invention provide a resource management mechanism to monitor the availability of resources, detect the cause of a rejection, distinguish between different types of rejections, and manage the different types accordingly. For example, a queue manager in accordance with embodiments of the invention may be able to classify rejected requests, for example, as either a “long reject” or a “short reject” based on the cause of the rejection and the amount of time the rejection conditions are expected to remain valid. A short reject request may be rescheduled in an appropriate service queue, while a long reject request may be suspended in a reject queue. Other features are described and claimed.Type: GrantFiled: December 30, 2005Date of Patent: June 7, 2011Assignee: Intel CorporationInventors: Abraham Mendelson, Julius Mandelblat, Larisa Novakovsky
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Patent number: 7949794Abstract: A method and apparatus for enhancing /extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.Type: GrantFiled: November 2, 2006Date of Patent: May 24, 2011Assignee: Intel CorporationInventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David Harriman, Mark Rosenbluth, Ajay Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert Blankenship, Ohad Fallk, Avi (Abraham) Mendelson, Ilan Pardo, Eran Tamari, Ellezer Weissmann, Doron Shamia
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Patent number: 7930566Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.Type: GrantFiled: October 31, 2007Date of Patent: April 19, 2011Assignee: Intel CorporationInventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David Harriman, Mark Rosenbluth, Ajay Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert Blankenship, Ohad Falik, Avi (Abraham) Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia
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Publication number: 20110072164Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.Type: ApplicationFiled: September 16, 2010Publication date: March 24, 2011Inventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David Harriman, Mark Rosenbluth, Ajay Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert Blankenship, Ohad Falik, Avi (Abraham) Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia
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Publication number: 20080215822Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.Type: ApplicationFiled: October 31, 2007Publication date: September 4, 2008Inventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David Harriman, Mark Rosenbluth, Ajay Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert Blankenship, Ohad Falik, Avi (Abraham) Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia
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Publication number: 20080195791Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.Type: ApplicationFiled: October 31, 2007Publication date: August 14, 2008Inventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David Harriman, Mark Rosenbluth, Ajay Bhatt, Peter Barry, Scott Dian Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert Blankenship, Ohad Falik, Avi (Abraham) Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia
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Patent number: 7412569Abstract: Briefly, a system and a method to efficiently track changes in memory or storage areas, for example, in cache memories of computers and electronic systems. A method in accordance with an exemplary embodiment of the invention includes, for example, updating a tracking list with an address and/or a corresponding address to be updated of a changed entry in an intermediate memory. A system in accordance with an exemplary embodiment of the invention may include, for example, a tracking unit to track the locations of potential data discrepancies between a reference memory and an intermediate memory.Type: GrantFiled: April 10, 2003Date of Patent: August 12, 2008Assignee: Intel CorporationInventors: Alon Naveh, Abraham Mendelson
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Patent number: 7260684Abstract: A cache management logistics controls a transfer of a trace. A first cache couples to the cache management logistics to evict the trace based on a replacement mechanism. A second cache couples to the cache management logistics to receive the trace based on a number of accesses to the trace.Type: GrantFiled: January 16, 2001Date of Patent: August 21, 2007Assignee: Intel CorporationInventors: Abraham Mendelson, Roni Rosner, Ronny Ronen
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Patent number: 7251811Abstract: In an embodiment, a method includes receiving a binary of a program code. The binary is based on a first instruction set architecture. The method also includes translating the binary, wherein the translated binary is based on a combination of the first instruction set architecture and a second instruction set architecture.Type: GrantFiled: January 2, 2002Date of Patent: July 31, 2007Assignee: Intel CorporationInventors: Roni Rosner, Abraham Mendelson
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Publication number: 20070157208Abstract: Embodiments of the present invention provide a resource management mechanism to monitor the availability of resources, detect the cause of a rejection, distinguish between different types of rejections, and manage the different types accordingly. For example, a queue manager in accordance with embodiments of the invention may be able to classify rejected requests, for example, as either a “long reject” or a “short reject” based on the cause of the rejection and the amount of time the rejection conditions are expected to remain valid. A short reject request may be rescheduled in an appropriate service queue, while a long reject request may be suspended in a reject queue. Other features are described and claimed.Type: ApplicationFiled: December 30, 2005Publication date: July 5, 2007Inventors: Abraham Mendelson, Julius Mandelblat, Larisa Novakovsky
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Publication number: 20070150663Abstract: Some embodiments of the invention provide devices, systems and methods of cache coherence. For example, an apparatus in accordance with an embodiment of the invention includes a memory to store a memory line; and a cache controller logic to assign a first cache coherence state to the memory line in relation to a first component, and to assign a second, different, cache coherence state to the memory line in relation to a second, different, component.Type: ApplicationFiled: December 27, 2005Publication date: June 28, 2007Inventors: Abraham Mendelson, Julius Mandelblat, Christopher Hughes, Daehyun Kim, Victor Lee, Anthony Nguyen, Yen-Kuang Chen
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Publication number: 20070022274Abstract: Embodiments of the invention provide a method that includes partitioning a series of instructions of a trace into a plurality of dependency sets before executing the trace; and marking a first group of the dependency sets as critical and a second group of the dependency sets as non-critical Embodiments of the invention also provide a method that may identify a dependency set in the second group, which delays the execution of at least one dependency set in the first group, as a delaying dependency set; counting the number of delays caused by the delaying dependency set; and re-marking the delaying dependency set as critical when a predefined delaying event threshold is reached.Type: ApplicationFiled: June 29, 2005Publication date: January 25, 2007Inventors: Roni Rosner, Ari Schmorak, Simcha Gochman, Abraham Mendelson, Guillermo Savransky
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Patent number: 7047395Abstract: A distributed system is provided for apportioning an instruction stream into multiple segments for processing in multiple parallel processing units, and for merging the processed segments into a single processed instruction stream having the same sequential relative order as the original instruction stream. Tags may be attached to each segment after apportioning to indicate the order in which the various segments are to be merged. In one embodiment, the end of each segment includes a tag indicating the unit to which the next instruction in the original instruction sequence is directed.Type: GrantFiled: November 13, 2001Date of Patent: May 16, 2006Assignee: Intel CorporationInventors: Roni Rosner, Micha G. Moffie, Abraham Mendelson
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Publication number: 20060053326Abstract: Systems and methods of managing processors provide for detecting a command at a core of a processor having a plurality of cores, where the command requests a transition of the core to an idle state. Power consumption of the core is managed based on the command and an idle state status of each of the plurality of cores.Type: ApplicationFiled: September 3, 2004Publication date: March 9, 2006Inventors: Alon Naveh, Abraham Mendelson, Ittai Anati, Eliezer Weissmann
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Publication number: 20040221138Abstract: A distributed system is provided for apportioning an instruction stream into multiple segments for processing in multiple parallel processing units, and for merging the processed segments into a single processed instruction stream having the same sequential relative order as the original instruction stream. Tags may be attached to each segment after apportioning to indicate the order in which the various segments are to be merged. In one embodiment, the end of each segment includes a tag indicating the unit to which the next instruction in the original instruction sequence is directed.Type: ApplicationFiled: November 13, 2001Publication date: November 4, 2004Inventors: Roni Rosner, Micha G. Moffie, Abraham Mendelson
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Publication number: 20040205303Abstract: Briefly, a system and a method to efficiently track changes in memory or storage areas, for example, in cache memories of computers and electronic systems. A method in accordance with an exemplary embodiment of the invention includes, for example, updating a tracking list with an address and/or a corresponding address to be updated of a changed entry in an intermediate memory. A system in accordance with an exemplary embodiment of the invention may include, for example, a tracking unit to track the locations of potential data discrepancies between a reference memory and an intermediate memory.Type: ApplicationFiled: April 10, 2003Publication date: October 14, 2004Inventors: Alon Naveh, Abraham Mendelson
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Publication number: 20030126587Abstract: In an embodiment, a method includes receiving a binary of a program code. The binary is based on a first instruction set architecture. The method also includes translating the binary, wherein the translated binary is based on a combination of the first instruction set architecture and a second instruction set architecture.Type: ApplicationFiled: January 2, 2002Publication date: July 3, 2003Inventors: Roni Rosner, Abraham Mendelson
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Publication number: 20020095553Abstract: A cache management logistics controls a transfer of a trace. A first cache couples to the cache management logistics to evict the trace based on a replacement mechanism. A second cache couples to the cache management logistics to receive the trace based on a number of accesses to the trace.Type: ApplicationFiled: January 16, 2001Publication date: July 18, 2002Inventors: Abraham Mendelson, Roni Rosner, Ronny Ronen
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Patent number: 5930830Abstract: A system and method are provided which significantly speed up the ability to reassemble network message transfer units (MTUs) using existing virtual memory systems. Discontiguous physical pages are rearranged in a continuous format in virtual memory by manipulating virtual page pointers in a hardware memory page table. The hardware memory page table provides any necessary virtual-to-real address translations during the execution of a process.Type: GrantFiled: January 13, 1997Date of Patent: July 27, 1999Assignee: International Business Machines CorporationInventors: Abraham Mendelson, Ronald Mraz, Lucas Aaron Womack