Abstract: A method of lead frame surface modification includes providing at least one pre-fabricated metal lead frame or package substrate (substrate) unit including a base metal having a die pad and a plurality of contact regions surrounding the die pad. An ink including a material that is a solid or a precursor for a solid that forms a solid upon a curing step or a sintering step that removes a liquid carrier is additively deposited including onto at least one of (i) a region of the die pad and (ii) at one region of at least a first of the contact regions (first contact region). The ink is sintered or cured to remove the liquid carrier so that a substantially solid ink residue remains.

Abstract: An assembly including an electrical connection substrate formed of material having a Young's modulus of less than about 10 MPa, an acoustic device die having opposite end portions mounted on and electrically connected to the electrical connection substrate and a mold compound layer encapsulating the acoustic device die and interfacing with the substrate.

Abstract: The assembly of a chip (101) attached to a substrate (103) with wires (201) spanning from the chip to the substrate is loaded in a heated cavity (402) of a mold; the wire surfaces are coated with an adsorbed layer of molecules of a heterocyclic compound (302); a pressure chamber (404) of the mold is loaded with a solid pellet (410) of a packaging material including a polymerizable resin, the chamber being connected to the cavity; the vapor of resin molecules is allowed to spread from the chamber to the assembly inside the cavity during the time interval needed to heat the solid pellet for rendering it semi-liquid and to pressurize it through runners (403) before filling the mold cavity, whereby the resin molecules arriving in the cavity are cross-linked by the adsorbed heterocyclic compound molecules into an electrically insulating at least one monolayer of polymeric structures on the wire surfaces.

Abstract: A chip is attached to a substrate with wires spanning from the chip to the substrate is loaded in a heated cavity of a mold. The wire surfaces are coated with an adsorbed layer of molecules of a heterocyclic compound. A pressure chamber of the mold is loaded with a solid pellet of a packaging material including a polymerizable resin. The chamber is connected to the cavity. The vapor of resin molecules is allowed to spread from the chamber to the assembly inside the cavity during the time interval needed to heat the solid pellet for rendering it semi-liquid and to pressurize it through runners before filling the mold cavity, wherein the resin molecules arriving in the cavity are cross-linked by the adsorbed heterocyclic compound molecules into an electrically insulating at least one monolayer of polymeric structures on the wire surfaces.

Abstract: The invention is directed to a method for inhibiting or preventing delamination at the interface of the die attach/mold compound and the die pad of a semiconductor device and a semiconductor device formed by such method. The method includes providing a leadframe having a top surface; coating said top surface of said leadframe with first and second silane coating; heating said silane coatings to form a pourous layer having a porosity of at least 10%; applying a die to said pourous layer; securing said die to said pourous layer by a die attaching compound; and after the curing of die attach material and wire bonding, a mold compound is applied through molding.

Abstract: A packaged semiconductor device (100) comprising a leadframe having a pad (101) with an assembled semiconductor chip (110), a plurality of straps (102) connecting the pad to side edges of the device package, leads (103), and a package (150) of plastic compound adhering to the leadframe; at least one surface (102a) of the straps covered with a layer (120) of a compound both non-adhesive to polymeric compounds and hydrophobic; the compound (220) selected from a group including fluorinated thiol compounds, fluorinated amine compounds, fluorinated aminesilanes, organosilanes, and their derivatives; or the compound (330) selected from a group including open-pore microcellular metal foams and polymer foams. Further, the package may include an array of holes through the plastic compound, extending from the package surface to the strap surface.

Abstract: A method of lead frame surface modification includes providing at least one pre-fabricated metal lead frame or package substrate (substrate) unit including a base metal having a die pad and a plurality of contact regions surrounding the die pad. An ink including a material that is a solid or a precursor for a solid that forms a solid upon a curing step or a sintering step that removes a liquid carrier is additively deposited including onto at least one of (i) a region of the die pad and (ii) at one region of at least a first of the contact regions (first contact region). The ink is sintered or cured to remove the liquid carrier so that a substantially solid ink residue remains.

Abstract: A flip chip light emitting diode (LED) package includes an LED die having a first substrate, a p-type region and an n-type region including an active layer in between, a metal contact on the p-type region (anode contact) and a metal contact on the n-type region (cathode contact). A package substrate or lead frame includes a dielectric material that has a first metal through via (first metal post) and second metal through via (second metal post) spaced apart from one another and embedded in the dielectric material. A first metal pad is on a bottom side of the first metal post and a second metal pad is on a bottom side of the second metal post. An interconnect metal paste or metal ink residual (metal residual) is between the anode contact and first metal post and between the cathode contact and the second metal post.

Abstract: The invention is directed to a method for inhibiting or preventing delamination at the interface of the die attach/mold compound and the die pad of a semiconductor device and a semiconductor device formed by such method. The method includes providing a leadframe having a top surface; coating said top surface of said leadframe with first and second silane coating; heating said silane coatings to form a sol-gel layer having a porosity of at least 10%; applying a die to said sol-gel layer; securing said die to said sol-gel layer by a die attaching compound; and after the curing of die attach material and wire bonding, a mold compound is applied through molding.

Abstract: Methods of fabricating integrated circuits are disclosed herein. A die having a side is provided. A conductive stud extends from the side in a direction that is substantially normal to the side. A first dielectric layer is affixed to the side of the die. The first dielectric layer has a first side and a second side. The first side of the first dielectric layer is affixed to the side of the die. The conductive stud pierces the first side of the first dielectric layer. A first via is formed through the first dielectric layer between the conductive stud and the second side. The first via is electrically connected to the conductive stud.

Abstract: Integrated circuits and methods of fabricating integrated circuits are disclosed herein. One embodiment of an integrated circuit includes a die having a side, wherein a conductive stud extends substantially normal relative to the side. A dielectric layer having a first side and a second side is located proximate the side of the die so that the first side of the dielectric layer is adjacent the side of the die. The conductive stud extends into the first side of the dielectric layer. A first via extends between the conductive stud and the second side of the dielectric layer. A conductive layer having a first side and a second side is located adjacent the second side of the dielectric layer, wherein the first side of the conductive layer is located adjacent the second side of the dielectric layer. At least a portion of the conductive layer is electrically connected to the first via.

Abstract: Methods of fabricating integrated circuits are disclosed herein. In one embodiment of a method. A die having a side is provided. A conductive stud is connected to the side of the die, wherein the conductive stud has a first end that is connected to the die and an opposite second end. The die is encapsulated said die except for the side. A first dielectric layer is affixed to the side of the die. The first dielectric layer has a first side and a second side. The first side of the first dielectric layer is affixed to the side of the die. The conductive stud enters the first side of the first dielectric layer. A conductive layer is affixed to the second side of the first dielectric layer. The second side of the conductive stud is affixed to the conductive layer using a conductive adhesive.

Abstract: A chip is attached to a substrate with wires spanning from the chip to the substrate is loaded in a heated cavity of a mold. The wire surfaces are coated with an adsorbed layer of molecules of a heterocyclic compound. A pressure chamber of the mold is loaded with a solid pellet of a packaging material including a polymerizable resin. The chamber is connected to the cavity. The vapor of resin molecules is allowed to spread from the chamber to the assembly inside the cavity during the time interval needed to heat the solid pellet for rendering it semi-liquid and to pressurize it through runners before filling the mold cavity, wherein the resin molecules arriving in the cavity are cross-linked by the adsorbed heterocyclic compound molecules into an electrically insulating at least one monolayer of polymeric structures on the wire surfaces.

Abstract: The packaging of an electric contact including a semiconductor chip (102) having terminals (101) of a first metal and connecting wires (111, 112) of a second metal, the wires forming at the terminals regions (113) of intermetallic compounds of the first and second metals; a solution of an aromatic azole compound dissolved in ethanol is dispensed onto the surfaces of the wire spans and the intermetallic regions, thereby forming on the surfaces layers (301) of adsorbed molecules of the aromatic azole compound; chip and wire bonds are encapsulated in a polymerizable resin (401), thereby exploiting the adsorbed aromatic azole molecules as catalysts to cross-link resin molecules into polymerized structures (402) having a mesh density capable of inhibiting the diffusion of impurity ions (410) and thus protecting the surface of the intermetallic regions.

Abstract: The assembly of a chip (101) attached to a substrate (103) with wires (201) spanning from the chip to the substrate is loaded in a heated cavity (402) of a mold; the wire surfaces are coated with an adsorbed layer of molecules of a heterocyclic compound (302); a pressure chamber (404) of the mold is loaded with a solid pellet (410) of a packaging material including a polymerizable resin, the chamber being connected to the cavity; the vapor of resin molecules is allowed to spread from the chamber to the assembly inside the cavity during the time interval needed to heat the solid pellet for rendering it semi-liquid and to pressurize it through runners (403) before filling the mold cavity, whereby the resin molecules arriving in the cavity are cross-linked by the adsorbed heterocyclic compound molecules into an electrically insulating at least one monolayer of polymeric structures on the wire surfaces.

Abstract: Integrated circuits and methods of fabricating integrated circuits are disclosed herein. One embodiment of an integrated circuit includes a die having a side, wherein a conductive stud extends from the side. A dielectric layer having a first side and a second side is located proximate the side of the die so that the first side of the dielectric layer is adjacent the side of the die. The conductive stud extends into the first side of the dielectric layer. A conductive layer having a first side and a second side is located adjacent the second side of the dielectric layer, wherein the first side of the conductive layer is located adjacent the second side of the dielectric layer. A conductive adhesive connects the conductive stud to the first side of the conductive layer.

Abstract: Integrated circuits and methods of fabricating integrated circuits are disclosed herein. One embodiment of an integrated circuit includes a die having a side, wherein a conductive stud extends substantially normal relative to the side. A dielectric layer having a first side and a second side is located proximate the side of the die so that the first side of the dielectric layer is adjacent the side of the die. The conductive stud extends into the first side of the dielectric layer. A first via extends between the conductive stud and the second side of the dielectric layer. A conductive layer having a first side and a second side is located adjacent the second side of the dielectric layer, wherein the first side of the conductive layer is located adjacent the second side of the dielectric layer. At least a portion of the conductive layer is electrically connected to the first via.

Abstract: Circuits and methods of fabricating circuits are disclosed herein. An embodiment of the circuit includes a die having a side, wherein a connection point is located on the side. A dielectric layer having a first side, a second side, and at least one via extending between the first side and the second side, is located proximate the side of the die. The via is electrically connected to the connection point. A conductive layer is located adjacent the second side of the first dielectric layer, wherein at least a portion of the conductive layer is electrically connected to the via.

Abstract: A semiconductor system (300) has one or more packaged active subsystems (310, 330); each subsystem has a substrate with electrical contact pads and one or more semiconductor chips stacked on top of each other, assembled on the substrate. The system further has a packaged passive subsystem (320) including a substrate with electrical contacts and passive electrical components, such as resistors, capacitors, and indictors. The passive subsystem is stacked with the active subsystems and connected to them by solder bodies.

Abstract: A semiconductor system (200) of one or more semiconductor interposers (201) with a certain dimension (210), conductive vias (212) extending from the first to the second surface, with terminals and attached non-reflow metal studs (215) at the ends of the vias. A semiconducting interposer surface may include discrete electronic components or an integrated circuit. One or more semiconductor chips (202, 203) have a dimension (220, 230) narrower than the interposer dimension, and an active surface with terminals and non-reflow metal studs (224, 234). One chip is flip-attached to the first interposer surface, and another chip to the second interposer surface, so that the interposer dimension projects over the chip dimension. An insulating substrate (204) has terminals and reflow bodies (242) to connect to the studs of the projecting interposer.