Patents by Inventor Abram M. Castro
Abram M. Castro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090258459Abstract: A semiconductor system (200) of one or more semiconductor interposers (201) with a certain dimension (210), conductive vias (212) extending from the first to the second surface, with terminals and attached non-reflow metal studs (215) at the ends of the vias. A semiconducting interposer surface may include discrete electronic components or an integrated circuit. One or more semiconductor chips (202, 203) have a dimension (220, 230) narrower than the interposer dimension, and an active surface with terminals and non-reflow metal studs (224, 234). One chip is flip-attached to the first interposer surface, and another chip to the second interposer surface, so that the interposer dimension projects over the chip dimension. An insulating substrate (204) has terminals and reflow bodies (242) to connect to the studs of the projecting interposer.Type: ApplicationFiled: June 17, 2009Publication date: October 15, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Mark A. GERBER, Kurt P. Wachtler, Abram M. Castro
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Patent number: 7573139Abstract: A semiconductor system (200) of one or more semiconductor interposers (201) with a certain dimension (210), conductive vias (212) extending from the first to the second surface, with terminals and attached non-reflow metal studs (215) at the ends of the vias. A semiconducting interposer surface may include discrete electronic components or an integrated circuit. One or more semiconductor chips (202, 203) have a dimension (220, 230) narrower than the interposer dimension, and an active surface with terminals and non-reflow metal studs (224, 234). One chip is flip-attached to the first interposer surface, and another chip to the second interposer surface, so that the interposer dimension projects over the chip dimension. An insulating substrate (204) has terminals and reflow bodies (242) to connect to the studs of the projecting interposer.Type: GrantFiled: May 12, 2008Date of Patent: August 11, 2009Assignee: Texas Instruments IncorporatedInventors: Mark A. Gerber, Kurt P. Wachtler, Abram M. Castro
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Patent number: 7569918Abstract: A semiconductor system (300) has one or more packaged active subsystems (310, 330); each subsystem has a substrate with electrical contact pads and one or more semiconductor chips stacked on top of each other, assembled on the substrate. The system further has a packaged passive subsystem (320) including a substrate with electrical contacts and passive electrical components, such as resistors, capacitors, and indictors. The passive subsystem is stacked with the active subsystems and connected to them by solder bodies.Type: GrantFiled: May 1, 2006Date of Patent: August 4, 2009Assignee: Texas Instruments IncorporatedInventors: Mark A. Gerber, Kurt P. Wachtler, Abram M. Castro
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Publication number: 20080315387Abstract: A semiconductor system (300) has one or more packaged active subsystems (310, 330); each subsystem has a substrate with electrical contact pads and one or more semiconductor chips stacked on top of each other, assembled on the substrate. The system further has a packaged passive subsystem (320) including a substrate with electrical contacts and passive electrical components, such as resistors, capacitors, and indictors. The passive subsystem is stacked with the active subsystems and connected to them by solder bodies.Type: ApplicationFiled: September 5, 2008Publication date: December 25, 2008Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Mark A. GERBER, Kurt P. WACHTLER, Abram M. CASTRO
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Publication number: 20080258286Abstract: A package-on-package system (100) has a first subsystem (191) interconnected with a second subsystem (192) by solder connectors (193). The first subsystem has an insulating, trace-laminated, sheet-like carrier (101), which is laminated (102) with an insulating trace-laminated frame (110) exposing a central portion (103) of the carrier. A first chip (160) is disposed in the central portion, with a second chip (170) on top; the height of the assembled chips approximates the frame height (111). Bondable contact pads (104) are in the central portion, and solderable terminals (121; pitch center-to-center 0.65 mm or less) on the frame. The second subsystem has a laminated substrate (194) with at least one chip (196) attached, and terminals (195) in locations matching the terminals (121) on the frame of the first subsystem. The terminals of both subsystems are interconnected with solder (193) of a higher reflow temperature than additional solder balls (190) for connecting to external parts.Type: ApplicationFiled: August 16, 2007Publication date: October 23, 2008Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Mark A. Gerber, Kurt P. Wachtler, Abram M. Castro
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Publication number: 20080246138Abstract: A semiconductor system (200) of one or more semiconductor interposers (201) with a certain dimension (210), conductive vias (212) extending from the first to the second surface, with terminals and attached non-reflow metal studs (215) at the ends of the vias. A semiconducting interposer surface may include discrete electronic components or an integrated circuit. One or more semiconductor chips (202, 203) have a dimension (220, 230) narrower than the interposer dimension, and an active surface with terminals and non-reflow metal studs (224, 234). One chip is flip-attached to the first interposer surface, and another chip to the second interposer surface, so that the interposer dimension projects over the chip dimension. An insulating substrate (204) has terminals and reflow bodies (242) to connect to the studs of the projecting interposer.Type: ApplicationFiled: May 12, 2008Publication date: October 9, 2008Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: MARK A. GERBER, KURT P. WACHTLER, ABRAM M. CASTRO
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Patent number: 7390700Abstract: A semiconductor system (200) of one or more semiconductor interposers (201) with a certain dimension (210), conductive vias (212) extending from the first to the second surface, with terminals and attached non-reflow metal studs (215) at the ends of the vias. A semiconducting interposer surface may include discrete electronic components or an integrated circuit. One or more semiconductor chips (202, 203) have a dimension (220, 230) narrower than the interposer dimension, and an active surface with terminals and non-reflow metal studs (224, 234). One chip is flip-attached to the first interposer surface, and another chip to the second interposer surface, so that the interposer dimension projects over the chip dimension. An insulating substrate (204) has terminals and reflow bodies (242) to connect to the studs of the projecting interposer.Type: GrantFiled: April 7, 2006Date of Patent: June 24, 2008Assignee: Texas Instruments IncorporatedInventors: Mark A. Gerber, Kurt P. Wachtler, Abram M. Castro
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Patent number: 6801438Abstract: A process for forming a circuit pattern on a substrate includes steps of forming a number of electrical circuits on a substrate, which circuits include an electrically conductive bus that interconnects the circuits, covering the electrical circuits with a soldermask, leaving electrical contact portions exposed, electroplating the exposed electrical contacts with a conductive surface finish by using the bus to electrolytically apply the surface finish, and then severing the bus at locations between circuits so that the circuits are electrically isolated from each other. The process may be used to make circuit boards and especially integrated circuit packages.Type: GrantFiled: October 24, 2000Date of Patent: October 5, 2004Assignee: Touch Future Technolocy Ltd.Inventor: Abram M. Castro
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Publication number: 20030183418Abstract: A circuit board according to the invention is made from two or more laminates each made of a fusible dielectric material, which laminates are bonded to each other along respective inner faces thereof. Each such laminate is preferably a pre-preg sheet containing both a heat-fusible resin and a reinforcing fiber filler to provide the desired stiffness and strength. A number of first electrical contacts are exposed on an outer face of the first laminate, and second electrical contacts are exposed on an outer face of the second laminate. The circuit board further includes a plurality of electrical conductors each running from a first contact to a second contact, the conductors including elongated conductive lines extending along one of the first or second laminates, and vias extending through the first and second laminates which have been filled with an electrically conductive via filler.Type: ApplicationFiled: June 9, 2003Publication date: October 2, 2003Inventors: Abram M. Castro, Bernardo Gallegos, Gary Lee Engvall
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Publication number: 20030132518Abstract: A package substrate suitable for use with a ball grid array according to the invention includes an electrically and thermally conductive heat sink having a top surface and a bottom surface, the heat sink having a slot formed therethrough which opens onto the top and bottom surfaces. A dielectric layer is formed on the bottom surface of the heat sink proximate the slot, preferably directly thereon without an intervening adhesive layer. A circuit is selectively formed in a circuit pattern on the dielectric layer. An electrically resistive soldermask is disposed on the dielectric layer and the circuit, which soldermask has openings therethrough which expose bond pads of the circuit. Such a substrate according to the invention permits the integrated circuit die to be mounted over the slot in the manner of a lead-on-chip package, but provides bond pads to which solder balls can be mounted in order to form a ball grid array.Type: ApplicationFiled: January 22, 2003Publication date: July 17, 2003Inventor: Abram M. Castro
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Publication number: 20030066679Abstract: A circuit board according to the invention is made from two or more laminates each made of a fusible dielectric material, which laminates are bonded to each other along respective inner faces thereof. Each such laminate is preferably a pre-preg sheet containing both a heat-fusible resin and a reinforcing fiber filler to provide the desired stiffness and strength. A number of first electrical contacts are exposed on an outer face of the first laminate, and second electrical contacts are exposed on an outer face of the second laminate. The circuit board further includes a plurality of electrical conductors each running from a first contact to a second contact, the conductors including elongated conductive lines extending along one of the first or second laminates, and vias extending through the first and second laminates which have been filled with an electrically conductive via filler.Type: ApplicationFiled: October 9, 2001Publication date: April 10, 2003Inventors: Abram M. Castro, Bernardo Gallegos, Gary Lee Engvall
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Patent number: 6534861Abstract: A package substrate suitable for use with a ball grid array according to the invention includes an electrically and thermally conductive heat sink having a top surface and a bottom surface, the heat sink having a slot formed therethrough which opens onto the top and bottom surfaces. A dielectric layer is formed on the bottom surface of the heat sink proximate the slot, preferably directly thereon without an intervening adhesive layer. A circuit is selectively formed in a circuit pattern on the dielectric layer. An electrically resistive soldermask is disposed on the dielectric layer and the circuit, which soldermask has openings therethrough which expose bond pads of the circuit. Such a substrate according to the invention permits the integrated circuit die to be mounted over the slot in the manner of a lead-on-chip package, but provides bond pads to which solder balls can be mounted in order to form a ball grid array.Type: GrantFiled: November 15, 1999Date of Patent: March 18, 2003Assignee: Substrate Technologies IncorporatedInventor: Abram M. Castro
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Patent number: 6501168Abstract: An enhanced ball grid array substrate package and method for manufacturing the same, where the substrate package includes a metal core having a first surface and a second surface opposite the first surface. The metal core further includes at least one cavity in which at least one integrated circuit is positioned. A dielectric layer is secured to the first surface of the metal core and includes at least one die cavity formed therein. Thereafter, a conductive seed layer is chemically deposited to exposed portions of the dielectric layer and the first surface of the metal core. Adjacent to the conductive seed layer, a circuit is electrolytically and selectively formed within a first circuit pattern.Type: GrantFiled: September 1, 1999Date of Patent: December 31, 2002Assignee: Substrate Technologies, IncorporatedInventors: Abram M. Castro, Aaron R. Castro
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Patent number: 6300165Abstract: A package substrate suitable for use with a ball grid array according to the invention includes an electrically and thermally conductive heat sink having a top surface and a bottom surface, the heat sink having a slot formed therethrough which opens onto the top and bottom surfaces. A dielectric layer is formed on the bottom surface of the heat sink proximate the slot, preferably directly thereon without an intervening adhesive layer. A circuit is selectively formed in a circuit pattern on the dielectric layer. An electrically resistive soldermask is disposed on the dielectric layer and the circuit, which soldermask has openings therethrough which expose bond pads of the circuit. Such a substrate according to the invention permits the integrated circuit die to be mounted over the slot in the manner of a lead-on-chip package, but provides bond pads to which solder balls can be mounted in order to form a ball grid array.Type: GrantFiled: January 18, 2001Date of Patent: October 9, 2001Assignee: Substrate Technologies IncorporatedInventor: Abram M. Castro
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Patent number: 6248612Abstract: An enhanced ball grid array substrate package and method for manufacturing the same, where the substrate package includes a metal core having a first surface and a second surface opposite the first surface. The metal core further includes at least one cavity in which at least one integrated circuit is positioned. A dielectric layer is secured to the first surface of the metal core and includes at least one die cavity formed therein. Thereafter, a conductive seed layer is chemically deposited to exposed portions of the dielectric layer and the first surface of the metal core. Adjacent to the conductive seed layer, a circuit is electrolytically and selectively formed within a first circuit pattern.Type: GrantFiled: August 18, 1999Date of Patent: June 19, 2001Assignee: Substrate Technologies, Inc.Inventors: Abram M. Castro, Aaron R. Castro
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Publication number: 20010002321Abstract: A package substrate suitable for use with a ball grid array according to the invention includes an electrically and thermally conductive heat sink having a top surface and a bottom surface, the heat sink having a slot formed therethrough which opens onto the top and bottom surfaces. A dielectric layer is formed on the bottom surface of the heat sink proximate the slot, preferably directly thereon without an intervening adhesive layer. A circuit is selectively formed in a circuit pattern on the dielectric layer. An electrically resistive soldermask is disposed on the dielectric layer and the circuit, which soldermask has openings therethrough which expose bond pads of the circuit. Such a substrate according to the invention permits the integrated circuit die to be mounted over the slot in the manner of a lead-on-chip package, but provides bond pads to which solder balls can be mounted in order to form a ball grid array.Type: ApplicationFiled: January 18, 2001Publication date: May 31, 2001Inventor: Abram M. Castro
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Patent number: 6107683Abstract: An enhanced ball grid array substrate package and method for manufacturing the same, where the substrate package includes a metal core having a first surface and a second surface opposite the first surface. The metal core further includes at least one cavity in which at least one integrated circuit is positioned. A dielectric layer is secured to the first surface of the metal core and includes at least one die cavity formed therein. Thereafter, a conductive seed layer is chemically deposited to exposed portions of the dielectric layer and the first surface of the metal core. Adjacent to the conductive seed layer, a circuit is electrolytically and selectively formed within a first circuit pattern.Type: GrantFiled: May 8, 1998Date of Patent: August 22, 2000Assignee: Substrate Technologies IncorporatedInventors: Abram M. Castro, Aaron R. Castro
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Patent number: 5650593Abstract: A thermally enhanced chip carrier package with a built-in heat sink for semi-conductor integrated circuit chips. A circuit substrate is formed of a suitable thermoplastic such as PPS or LCP with a center opening and a metal attachment ring for attaching a heat sink to either the top or bottom thereof with solder. A casing is further formed on the substrate outwardly of the aperture and the heat sink mounted thereacross, the casing being comprised of the suitable thermoplastic and being chemically fused to a portion of the circuit substrate to create a moisture seal therebetween. An encapsulant for filling the cavity within the casing and a lid may also be utilized to further secure and seal the chip mounted to the heat sink secured therein.Type: GrantFiled: February 6, 1995Date of Patent: July 22, 1997Assignee: Amkor Electronics, Inc.Inventors: John R. McMillan, William H. Maslakow, Abram M. Castro