Abstract: A lateral high-voltage transistor includes a semiconductor substrate, a body region formed by dopant implantation in the semiconductor substrate, the body region having a lateral boundary, a dielectric layer arranged over the semiconductor substrate, and a structured gate layer arranged over the dielectric layer. The structured gate layer overlaps the body region in the semiconductor substrate in a zone between the lateral boundary of the body region and a gate edge of the structured gate layer. The lateral boundary of the body region is a boundary defined by dopant implantation.

Abstract: A method of manufacturing a lateral transistor is described. The method includes providing a semiconductor substrate. A dielectric layer is formed over the semiconductor substrate. A gate layer is formed over the dielectric layer. A photoresist layer is applied over the gate layer. The photoresist layer is opened by lithography to form a first opening of a first opening size in the photoresist layer. The first opening is transferred into a second opening of a second opening size, the second opening being either formed in the photoresist layer or in an auxiliary layer. A body region is formed in the semiconductor substrate by dopant implantation. Further the gate layer is structured to form a gate edge. An overlap between the structured gate layer and the body region is controlled by an offset between the first opening size and the second opening size.

Abstract: A method of manufacturing a lateral transistor is described. The method includes providing a semiconductor substrate. A dielectric layer is formed over the semiconductor substrate. A gate layer is formed over the dielectric layer. A photoresist layer is applied over the gate layer. The photoresist layer is opened by lithography to form a first opening of a first opening size in the photoresist layer. The first opening is transferred into a second opening of a second opening size, the second opening being either formed in the photoresist layer or in an auxiliary layer. A body region is formed in the semiconductor substrate by dopant implantation. Further the gate layer is structured to form a gate edge. An overlap between the structured gate layer and the body region is controlled by an offset between the first opening size and the second opening size.

Abstract: A fuse arrangement, including: at least a first terminal, a second terminal, and a fuse, wherein the first terminal and the second terminal may be electrically connected via the fuse, and wherein the fuse may be configured to be under fuse internal mechanical stress to deform the fuse along its width direction in case it is broken.

Abstract: A fuse arrangement, including: at least a first terminal, a second terminal, and a fuse, wherein the first terminal and the second terminal may be electrically connected via the fuse, and wherein the fuse may be configured to be under fuse internal mechanical stress to deform the fuse along its width direction in case it is broken.

Abstract: A fuse arrangement, including: at least a first terminal, a second terminal, and a fuse, wherein the first terminal and the second terminal may be electrically connected via the fuse, and wherein the fuse may be configured to be under fuse internal mechanical stress to deform the fuse along its width direction in case it is broken.

Abstract: A method of processing a semiconductor wafer includes forming semiconductor dies in the semiconductor wafer, each die having an active region containing devices of an integrated circuit and an edge region surrounding the active region, adjacent ones of the dies being separated by a scribe line. The method further includes forming interconnect wiring over the active region of each semiconductor die in an interlayer dielectric, forming ancillary wiring over the edge region of each die in the interlayer dielectric, forming a passivation on the interlayer dielectric, forming bond pads over the interconnect wiring of each die, the bond pads of each die being in electrical connection with the interconnect wiring of that die, and forming additional bond pads over the ancillary wiring of each semiconductor die, the additional bond pads of each die being in electrical connection with the interconnect wiring of that die.

Abstract: According to various embodiments, a semiconductor substrate arrangement may be provided, wherein the semiconductor substrate arrangement may include: a semiconductor substrate defining a first area at a first level and a second area next to the first area at a second level, wherein the first level is lower than the second level; a plurality of planar non-volatile memory structures disposed over the semiconductor substrate in the first area; and a plurality of planar transistor structures disposed over the semiconductor substrate in the second area.

Abstract: A semiconductor device and method of making a semiconductor device are disclosed. A semiconductor body, a floating gate poly and a source/drain region are provided. A metal interconnect region with a control gate node is provided that capacitively couples to the floating gate poly.

Abstract: A method of processing a semiconductor wafer includes forming semiconductor dies in the semiconductor wafer, each die having an active region containing devices of an integrated circuit and an edge region surrounding the active region, adjacent ones of the dies being separated by a scribe line. The method further includes forming interconnect wiring over the active region of each semiconductor die in an interlayer dielectric, forming ancillary wiring over the edge region of each die in the interlayer dielectric, forming a passivation on the interlayer dielectric, forming bond pads over the interconnect wiring of each die, the bond pads of each die being in electrical connection with the interconnect wiring of that die, and forming additional bond pads over the ancillary wiring of each semiconductor die, the additional bond pads of each die being in electrical connection with the interconnect wiring of that die.

Abstract: A semiconductor device and method of making a semiconductor device are disclosed. A semiconductor body, a floating gate poly and a source/drain region are provided. A metal interconnect region with a control gate node is provided that capacitively couples to the floating gate poly.

Abstract: A semiconductor die includes a semiconductor substrate having an edge region surrounding an active region, the active region containing devices of an integrated circuit. The semiconductor die further includes interconnect wiring over the active region in an interlayer dielectric and electrically connected to the devices in the active region, and ancillary wiring over the edge region in the interlayer dielectric and isolated from the interconnect wiring and the devices in the active device region. The interlayer dielectric is passivated, and bond pads are provided over the interconnect wiring and electrically connected to the interconnect wiring through openings in the passivation over the active region. Additional bond pads are provided over the ancillary wiring and are electrically connected to the interconnect wiring through additional openings in the passivation over the active region.

Abstract: A wafer has a number of IC areas and a kerf area arranged between the IC areas. The kerf area has a dicing area, a crack stop structure arranged between an IC area and a dicing area, and a trench arranged between the crack stop structure and the dicing area. The crack stop structure includes an extended layer extending beyond the crack stop structure towards the dicing area.

Abstract: A semiconductor device and method of making a semiconductor device are disclosed. A semiconductor body, a floating gate poly and a source/drain region are provided. A metal interconnect region with a control gate node is provided that capacitively couples to the floating gate poly.

Abstract: A fuse arrangement, including: at least a first terminal, a second terminal, and a fuse, wherein the first terminal and the second terminal may be electrically connected via the fuse, and wherein the fuse may be configured to be under fuse internal mechanical stress to deform the fuse along its width direction in case it is broken.

Abstract: A wafer has a number of IC areas and a kerf area arranged between the IC areas. The kerf area has a dicing area, a crack stop structure arranged between an IC area and a dicing area, and a trench arranged between the crack stop structure and the dicing area. The crack stop structure includes an extended layer extending beyond the crack stop structure towards the dicing area.

Abstract: A semiconductor device and method of making a semiconductor device are disclosed. A semiconductor body, a floating gate poly and a source/drain region are provided. A metal interconnect region with a control gate node is provided that capacitively couples to the floating gate poly.

Abstract: A semiconductor device and method of making a semiconductor device are disclosed. A semiconductor body, a floating gate poly and a source/drain region are provided. A metal interconnect region with a control gate node is provided that capacitively couples to the floating gate poly.

Abstract: A detector includes a first semiconductor substrate and a second substrate, wherein the first semiconductor substrate includes a detector element for detecting a radiation or a particle and the second substrate includes a control circuit. The detector element extends from a first main surface of the first semiconductor substrate to a second main surface of the first semiconductor substrate.

Abstract: A detector includes a first semiconductor substrate and a second substrate, wherein the first semiconductor substrate includes a detector element for detecting a radiation or a particle and the second substrate includes a control circuit. The detector element extends from a first main surface of the first semiconductor substrate to a second main surface of the first semiconductor substrate.