Abstract: Methods of selectively forming nanocrystals on semiconductor devices are disclosed. Regions of a workpiece are masked with a masking material, and the nanocrystals are formed on the unmasked regions. The nanocrystals may be formed by exposing the masked workpiece to a first substance, and exposing the workpiece to at least one second substance either before or after the masking material is removed.

Abstract: A via structure is disclosed for use in a multi-layered semiconductor device, for forming electrical contacts between prescribed layers of the vertically aligned structures. The via structures include a plurality of adjacent frame shaped hole structures which extend between the prescribed layers of the device, and which are filled with metal to form frame shaped vias. The width of each of the sides of the frame is chosen to be equal to an integer multiple of half of the minimum pitch of the semiconductor processing, with the distance between adjacent frame shaped via structures being approximately equal to an integer multiple of half of the minimum pitch of the semiconductor processing.

Abstract: A semiconductor device can be fabricated by forming a floating gate layer over a semiconductor body. The floating gate layer is at least partially arranged over an insulation region in the semiconductor body. The floating gate layer is patterned to expose a portion of the insulation region. A recess is formed in a portion of the insulation region exposed by the patterned floating gate layer. A conductor is deposited within the recess. The conductor serves as a buried bitline. An insulator can then be formed within the recess over the conductor.

Abstract: A semiconductor device and method of making a semiconductor device are disclosed. A semiconductor body, a floating gate poly and a source/drain region are provided. A metal interconnect region with a control gate node is provided that capacitively couples to the floating gate poly.

Abstract: An explanation is given of, inter alia, a circuit arrangement containing a trench which penetrates through a charge-storing layer (18) and a doped semiconductor layer (14). The trench simultaneously fulfils a multiplicity of functions, namely an insulating function between adjacent components, the patterning of the charge-storing layer and also the subdivision of doping layers of the semiconductor layer (14).

Abstract: A via structure is disclosed for use in a multi-layered semiconductor device, for forming electrical contacts between prescribed layers of the vertically aligned structures. The via structures include a plurality of adjacent frame shaped hole structures which extend between the prescribed layers of the device, and which are filled with metal to form frame shaped vias. The width of each of the sides of the frame is chosen to be equal to an integer multiple of half of the minimum pitch of the semiconductor processing, with the distance between adjacent frame shaped via structures being approximately equal to an integer multiple of half of the minimum pitch of the semiconductor processing.

Abstract: A flash memory cell can be read by selecting a local bit line. A read potential is applied to a memory cell transistor associated with the local bit line thereby generating a capacitive loading of the local bit line. The capacitive loading depends upon a magnitude of charge stored on a floating gate of the memory cell transistor. The capacitive loading of the local bit line can then be assessed to determine a state of the memory cell transistor, the state being related to the magnitude of the charge stored on the floating gate.

Abstract: The invention considers a non-volatile semiconductor memory device comprising a first and second floating gate transistor, which are coupled in series. Each floating gate transistor comprises a floating gate. Programming means coupled to the first and second floating gate transistor are operable to place a selected electrical charge in one of the floating gates and less than the selected electrical charge in the other floating gate to represent either a first or second binary value.

Abstract: An explanation is given of, inter alia, a circuit arrangement containing a trench which penetrates through a charge-storing layer (18) and a doped semiconductor layer (14). The trench simultaneously fulfils a multiplicity of functions, namely an insulating function between adjacent components, the patterning of the charge-storing layer and also the subdivision of doping layers of the semiconductor layer (14).

Abstract: Methods of selectively forming nanocrystals on semiconductor devices are disclosed. Regions of a workpiece are masked with a masking material, and the nanocrystals are formed on the unmasked regions. The nanocrystals may be formed by exposing the masked workpiece to a first substance, and exposing the workpiece to at least one second substance either before or after the masking material is removed.

Abstract: A class D power output stage for switching a supply voltage comprises a limiting transistor with a controllable path and a control terminal, a complementary limiting transistor with a controllable path and a control terminal, a switching transistor with a controllable path and a control terminal, and a complementary switching transistor with a controllable path and a control terminal. A switched output signal between the controllable paths of the limiting and complementary limiting transistors can be taped off, the controllable paths of the limiting and the complementary limiting transistors are connected together and are connected to a first and a second supply terminal via the controllable paths of the switching and complementary switching transistors, and the switching and the complementary switching transistors have a lower electrical strength than the limiting and complementary limiting transistors.

Abstract: A source connection of a field effect transistor is formed using a contact region, which adjoins a source region, is highly oppositely doped and forms a butting contact with the source region. A well or substrate connecting region which is electrically conductively connected to a supply potential lead is arranged separately from the contact region in the semiconductor material.

Abstract: An explanation is given of, inter alia, a circuit arrangement containing a trench which penetrates through a charge-storing layer (18) and a doped semiconductor layer (14). The trench simultaneously fulfils a multiplicity of functions, namely an insulating function between adjacent components, the patterning of the charge-storing layer and also the subdivision of doping layers of the semiconductor layer (14).

Abstract: The invention considers a non-volatile semiconductor memory device comprising a first and second floating gate transistor, which are coupled in series. Each floating gate transistor comprises a floating gate. Programming means coupled to the first and second floating gate transistor are operable to place a selected electrical charge in one of the floating gates and less than the selected electrical charge in the other floating gate to represent either a first or second binary value.

Abstract: In a method for fabricating a buried bit line for a semiconductor memory, the buried bit line is produced as a diffusion region using a dopant source including polysilicon that has previously been applied above the region intended for the buried bit line. This keeps the extent of diffusion within limits and means that the doped polysilicon is particularly suitable for the formation of the insulating oxide region above the buried bit line, due to the rapid oxidation.

Abstract: A flash memory cell can be read by selecting a local bit line. A read potential is applied to a memory cell transistor associated with the local bit line thereby generating a capacitive loading of the local bit line. The capacitive loading depends upon a magnitude of charge stored on a floating gate of the memory cell transistor. The capacitive loading of the local bit line can then be assessed to determine a state of the memory cell transistor, the state being related to the magnitude of the charge stored on the floating gate.

Abstract: A semiconductor device can be fabricated by forming a floating gate layer over a semiconductor body. The floating gate layer is at least partially arranged over an insulation region in the semiconductor body. The floating gate layer is patterned to expose a portion of the insulation region. A recess is formed in a portion of the insulation region exposed by the patterned floating gate layer. A conductor is deposited within the recess. The conductor serves as a buried bitline. An insulator can then be formed within the recess over the conductor.

Abstract: An explanation is given of, inter alia, a circuit arrangement containing a trench which penetrates through a charge-storing layer (18) and a doped semiconductor layer (14). The trench simultaneously fulfils a multiplicity of functions, namely an insulating function between adjacent components, the patterning of the charge-storing layer and also the subdivision of doping layers of the semiconductor layer (14).

Abstract: Each memory cell is a memory transistor which is provided on a top side of a semiconductor body and has a gate electrode which is arranged in a trench located between a source region and a drain region that are formed in the semiconductor material. The gate electrode is separated from the semiconductor material by a dielectric material. At least between the source region and the gate electrode and between the drain region and the gate electrode, there is an oxide-nitride-oxide layer sequence. The layer sequence is provided for the purpose of trapping charge carriers at the source and the drain.

Abstract: A vertical non-volatile semiconductor memory cell and an associated manufacturing method in which a trench extension, which has a third dielectric layer and a filler material, is formed underneath the vertical semiconductor memory cell with its first dielectric layer, its charge storage layer, its second dielectric layer and its control layer. In this way, the data retention properties and a coupling factor are improved.