Abstract: Provided are a memory controller, system, and method for generating multi-plane reads to read pages on planes of a storage die for a page to read. A memory controller determines planes for a read to a page. A storage die of the storage dies includes a plurality of planes having a plurality of blocks and the blocks have pages. The page to read is implemented in pages on the planes. The memory controller determines threshold voltages for the pages in the determined planes and determines a derived threshold voltage from the determined threshold voltages. The derived threshold voltage is used to perform multi-plane reads of the pages from the determined planes.

Abstract: A computer-implemented method, according to one embodiment, includes: receiving, in first and second read request buffers corresponding to first and second computer interface links of a data storage system, read requests. Read completion data corresponding to the read requests being performed is also received. The read completion data is allocated between first and second read completion buffers based on which of the read completion buffers has a greater amount of available space therein. Furthermore, the read completion data in the first and second read completion buffers is sent. The first read completion buffer corresponds to the first computer interface link and the second read completion buffer corresponds to the second computer interface link.

Abstract: A computer-implemented method, according to one embodiment, is for performing garbage collection. The computer-implemented method includes: causing pages in non-volatile memory that are due for garbage collection to be inspected, and causing certain ones of the pages in the non-volatile memory having valid data therein to be identified. Each of the pages of non-volatile memory includes multiple planes, and the valid data is included in one or more of the planes in the respective identified pages. Recirculation requests, that selectively exclude planes in the identified pages that do not include any of the valid data, are further sent to a recirculation pool.

Abstract: Provided are a memory controller, system, and method for generating multi-plane reads to read pages on planes of a storage die for a page to read. A memory controller determines planes for a read to a page. A storage die of the storage dies includes a plurality of planes having a plurality of blocks and the blocks have pages. The page to read is implemented in pages on the planes. The memory controller determines threshold voltages for the pages in the determined planes and determines a derived threshold voltage from the determined threshold voltages. The derived threshold voltage is used to perform multi-plane reads of the pages from the determined planes.

Abstract: A computer-implemented method, according to one embodiment, includes: receiving, in first and second read request buffers corresponding to first and second computer interface links of a data storage system, read requests. Read completion data corresponding to the read requests being performed is also received. The read completion data is allocated between first and second read completion buffers based on which of the read completion buffers has a greater amount of available space therein. Furthermore, the read completion data in the first and second read completion buffers is sent. The first read completion buffer corresponds to the first computer interface link and the second read completion buffer corresponds to the second computer interface link.

Abstract: A data storage system provides persistent storage in bulk non-volatile memory. A controller of the data storage system receives a host write command and buffers associated host write data in both a first write cache in non-volatile memory and a mirrored second write cache in volatile memory. The controller destages the host write data to the bulk non-volatile memory from the second write cache but not the first write cache. The controller services relocation write commands requesting data relocation within the bulk non-volatile memory by reference to the second write cache. Servicing the relocation write commands includes buffering relocation write data in the second write cache but not the first write cache and destaging the relocation write data to the bulk non-volatile memory from the second write cache.

Abstract: A data storage system provides persistent storage in bulk non-volatile memory. A controller of the data storage system receives a host write command and buffers associated host write data in both a first write cache in non-volatile memory and a mirrored second write cache in volatile memory. The controller destages the host write data to the bulk non-volatile memory from the second write cache but not the first write cache. The controller services relocation write commands requesting data relocation within the bulk non-volatile memory by reference to the second write cache. Servicing the relocation write commands includes buffering relocation write data in the second write cache but not the first write cache and destaging the relocation write data to the bulk non-volatile memory from the second write cache.

Abstract: A mechanism for temporarily stalling selected Direct Memory Access (DMA) operations in a physical input/output (I/O) adapter in order to permit migration of data between physical pages that are subject to access by the physical I/O adapter. When a request for a DMA to a physical page in system memory is received from an I/O adapter, a migration in progress (MIP) bit in a translation control entry (TCE) pointing to the physical page is examined, wherein the MIP bit indicates whether migration of the physical page referenced in the TCE to another location in system memory is currently in progress. If the MIP bit indicates a migration of the physical page is in progress, the DMA from the I/O adapter is temporarily stalled while other DMA operations from other I/O adapters to other physical pages in system memory are allowed to continue.

Abstract: A computer-implemented method, apparatus, and computer program product are disclosed for migrating data from a source physical page to a destination physical page. A migration process is begun to migrate data from the source physical page to the destination physical page which causes a host bridge to enter a first state. The host bridge then suspends processing of direct memory access operations when the host bridge is in the first state. The data is migrated from the source physical page to the destination physical page while the host bridge is in the first state.

Abstract: A computer-implemented method, apparatus, and computer program product are disclosed for migrating data from a source physical page to a destination physical page. A migration process is begun to migrate data from the source physical page to the destination physical page which causes a host bridge to enter a first state. The host bridge then suspends processing of direct memory access operations when the host bridge is in the first state. The data is migrated from the source physical page to the destination physical page while the host bridge is in the first state.

Abstract: Embodiments are provided in which a method is described for transferring data in a digital system comprising a first bus, a second bus, and a bridge coupling the first and second buses. During system initialization, an initialization program collects system information of the digital system. Then, based on the system information of the digital system, the initialization program determines a buffered packet size and configures the bridge with the buffered packet size. After system initialization, the bridge transfers data from the first bus to the second bus via the bridge according to the buffered packet size.

Abstract: Embodiments are provided in which clock generation for a PCI bridge and its N attached secondary buses is carried out by using an external PLL clock generator which generates N+1 first clock signals at a first frequency to the bridge and to N multiplexers. The bridge in turn generates N second clock signals to the N multiplexers. Each of the N clock signals generated by the bridge can be at either a second or third frequency. Each of the N multiplexers passes one of the first clock signal and second clock signal to a secondary bus depending on the speed of the slowest adapter on the secondary bus.

Abstract: Embodiments are provided in which a method is described for transferring data in a digital system including a first bus, a second bus, a PCI-X bridge coupling the first and second buses, and a first device and a second device residing on the first and second buses, respectively. The first bus has the same or higher bandwidth than that of the second bus. According to the method, the PCI-X bridge immediately starts or resumes forwarding split completion data from the first device to the second device if the first device starts or resumes split completion data transfer to the PCI-X bridge at the beginning of a block (i.e., the start or resume byte address has the form of 128N). If the first device starts transfer to the PCI-X bridge not at the beginning of a block, the PCI-X bridge refrains from forwarding split completion data until (a) the first device sends the data byte at the beginning of the next block to the PCI-X bridge or (b) the byte transfer count is exhausted, whichever occurs first.

Abstract: A packet memory system is provided. The packet memory system includes a memory cell array for storing a predefined number of packets. Each packet includes a predetermined number of segments. Each of the segments defines a starting point of a memory access. A packet decoder coupled to the memory cell array receives packet select inputs for selecting a packet. A segment decoder coupled to the memory cell array receives segment select inputs for selecting a segment. A data flow multiplexer is coupled to the memory cell array for transferring data between a data bus and the memory cell array. Command and mode registers receive command, read/write (R/W) and chip select (CS) inputs for opening a packet. Responsive to an opened packet, the packet select inputs provide a length for the memory access. Each of the segments has a preprogrammed length. Also each of the segments can be defined for a cache line.

Abstract: A split operation such as a split read or a split write is handled by a bus bridge circuit. The bus bridge receives the read or write command from a requesting device, where the command includes a bus number for routing a completion of the command. The bus bridge then compares the bus number received from the requesting device with the return route bus number range of the bus bridge, and issues a split response to the requesting device if the bus number matches the return route bus number range of the bus bridge. If the bus number does not match the return route bus number range, then the command is aborted.

Abstract: A method and implementing system is provided in which multiple nodes of a Peripheral Component Interconnect PCI bridge/router circuit are connected to corresponding plurality of PCI busses to enable an extended number of PCI adapters to be connected within a computer system. Multiple enhanced arbiters are implemented to enable non-blocking and deadlock-free operation while still complying with PCI system requirements. An exemplary PCI-to-PCI router (PPR) circuit includes the arbiters as well as PPR buffers for temporarily storing transaction-related information passing through the router circuit between adapters on the PCI busses and/or between PCI adapters and the CPUs and system memory or other system devices. A buffer re-naming methodology is implemented to eliminate internal request/completion transaction information transfers between bridge buffers thereby increasing system performance.

Abstract: A method, system, and apparatus for modifying bridges within a data processing system to provide improved performance is provided. In one embodiment, the data processing system determines the number of input/output adapters connected underneath each PCI host bridge. The data processing system also determines the type of each input/output adapter. The size and number of buffers within the PCI host bridge is then modified based on the number of adapters beneath it as well as the type of adapters beneath it to improve data throughput performance as well as prevent thrashing of data. The PCI host bridge is also modified to give load and store operations priority over DMA operations. Each PCI-to-PCI bridge is modified based on the type of adapter connected to it such that the PCI-to-PCI bridge prefetches only an amount of data consistent with the type of adapter such that excess data is not thrashed, thus requiring extensive repetitive use of the system buses to retrieve the same data more than once.

Abstract: Embodiments are provided in which a method is described for transferring data in a digital system comprising a first bus, a second bus, and a bridge coupling the first and second buses. During system initialization, an initialization program collects system information of the digital system. Then, based on the system information of the digital system, the initialization program determines a buffered packet size and configures the bridge with the buffered packet size. After system initialization, the bridge transfers data from the first bus to the second bus via the bridge according to the buffered packet size.

Abstract: Embodiments are provided in which a method is described for transferring data in a digital system including a first bus, a second bus, a PCI-X bridge coupling the first and second buses, and a first device and a second device residing on the first and second buses, respectively. The first bus has the same or higher bandwidth than that of the second bus. According to the method, the PCI-X bridge immediately starts or resumes forwarding split completion data from the first device to the second device if the first device starts or resumes split completion data transfer to the PCI-X bridge at the beginning of a block (i.e., the start or resume byte address has the form of 128N).

Abstract: A split operation such as a split read or a split write is handled by a bus bridge circuit. The bus bridge receives the read or write command from a requesting device, where the command includes a bus number for routing a completion of the command. The bus bridge then compares the bus number received from the requesting device with the return route bus number range of the bus bridge, and issues a split response to the requesting device if the bus number matches the return route bus number range of the bus bridge. If the bus number does not match the return route bus number range, then the command is aborted.