Abstract: Embodiments are provided in which clock generation for a PCI bridge and its N attached secondary buses is carried out by using an external PLL clock generator which generates N+1 first clock signals at a first frequency to the bridge and to N multiplexers. The bridge in turn generates N second clock signals to the N multiplexers. Each of the N clock signals generated by the bridge can be at either a second or third frequency. Each of the N multiplexers passes one of the first clock signal and second clock signal to a secondary bus depending on the speed of the slowest adapter on the secondary bus.

Abstract: A system and method for optimally processing split request transactions across a PCI-X bridge with a PCI-X bridge buffer. The split transaction mode of the PCI-X bridge buffer is toggled between a No Over-commit mode and an over-commit mode. Over-commitment of the buffer is inhibited when the split transaction mode is toggled to the No Over-commit mode and when the buffer is over committed by the bridge. At least some over-commitment of the buffer is allowed by the bridge when the split transaction mode is toggled to the over-commit mode and when the buffer is not over committed by the bridge. The over-commit mode may be an Over-commitment mode or a Flood mode. The Over-commitment mode allows some degree of over commitment of the buffer by the bridge while the Flood mode allows the bridge to forward all split request transactions regardless of size of the transactions or amount of available space in the buffer when the Over-commit mode is in a Flood mode.

Abstract: A PCI host bridge and an associated method of use are disclosed. The PCI host bridge includes a host bus interface, an I/O bus interface, and a PCI operation detection circuit. The host bus interface is suitable for communicating with a host bus of a data processing system and the I/O bus interface is suitable for communicating with a primary PCI bus operating in PCI-X mode. The PCI operation detection circuit is adapted to detect a PCI-X operation from the primary PCI bus that may have issued from a PCI mode adapter coupled to a secondary PCI bus. The detection circuit is further adapted to generate a modified operation for forwarding to the host bus in response to determining that the PCI-X operation may have originated from a PCI. mode adapter.

Abstract: A method and apparatus are provided for implementing peripheral component interconnect (PCI) combining function for PCI bridges. A programmable boundary for a combined operation is selected. A write request is received. Responsive to the write request, checking for a combined operation hit is performed. Responsive to an identified combined operation hit, a combined operation is accepted. Checking for the selected programmable boundary for the combined operation is performed. Responsive to identifying the programmable boundary for the combined operation, the combined operation is launched to a destination bus. A programmable timer is identified for the combined operation. Responsive to the programmable timer expiring, the combined operation is launched to a destination bus.

Abstract: A method and apparatus are provided for implementing error injection for peripheral component interconnect (PCI) bridges. The apparatus for implementing error injection for peripheral component interconnect (PCI) bridges includes a plurality of PCI busses and a control logic coupled to the plurality of PCI busses. The control logic targets a selected bus of the plurality of PCI busses. A hit is detected on the selected bus. Responsive to the detected hit, an error is injected on the selected bus. For a detected hit for predefined bug types, the operation must match a selected read or write, target or master, command type and the address must match unmasked address bits. For a detected hit for another predefined bug type, the PCI data bus must also match an unmask data register.

Abstract: A method and implementing system are provided in which multiple nodes of a PCI bridge/router circuit are connected to corresponding plurality of PCI busses to enable an extended number of PCI adapters to be connected within a computer system. An exemplary PCI-to-PCI router (PPR) circuit includes the arbiters as well as PPR buffers for temporarily storing transaction-related information passing through the router circuit between adapters on the PCI busses and/or between PCI adapters and the CPUs and system memory or other system devices. A buffer re-naming methodology is implemented to eliminate internal request/completion transaction information transfers between bridge buffers thereby increasing system performance.

Abstract: A method and implementing system is provided in which multiple nodes of a PCI bridge/router circuit are connected to corresponding plurality of PCI busses to enable an extended number of PCI adapters to be connected within a computer system. Multiple enhanced arbiters are implemented to enable non-blocking and deadlock-free operation while still complying with PCI system requirements. An exemplary PCI-to-PCI router (PPR) circuit includes the arbiters as well as PPR buffers for temporarily storing transaction-related information passing through the router circuit between adapters on the PCI busses and/or between PCI adapters and the CPUs and system memory or other system devices. A buffer re-naming methodology is implemented to eliminate internal request/completion transaction information transfers between bridge buffers thereby increasing system performance.

Abstract: A method and implementing system is provided in which system bridge circuits are enabled to execute, or over-commit to, transaction requests from system devices for information transfers which exceed the bridge circuit's current capacity to receive the requested information on its return from a designated target device such as system memory or another system device. The transaction request is moved along the data path to the designated target device and the requested information is returned, in an example, to the requesting device. By the time the requested information is returned to the requesting bridge circuit, a number of the holding buffers usually have been freed-up and are available to accept and pass the information to the requesting device.

Abstract: Buffer management for improved PCI-X or PCI bridge performance. A system and method for managing transactions across a PCI-X or PCI bridge, and a system and method of waiting for, increasing, and/or optimizing the available buffers for transaction size or sizes across a PCI-X or PCI bridge. Transactions are processed across the bridge, and the bridge has buffers with actual available buffer space used for receiving and processing the transactions. Transaction size of the transaction is determined. The system and method sets an available free block which is a set amount of available buffer space that is to be freed up before certain larger size transactions are processed. The system and method waits for the actual available buffer space to free up to and reach the available free block. The certain larger size transactions are then processed when the actual available buffer space has reached the available free block.

Abstract: A method and implementing system is provided in which multiple nodes of a PCI bridge/router circuit are connected to corresponding plurality of PCI busses to enable an extended number of PCI adapters to be connected within a computer system. Multiple enhanced arbiters are implemented to enable non-blocking and deadlock-free operation while still complying with PCI system requirements. An exemplary PCI-to-PCI router (PPR) circuit includes the arbiters as well as PPR buffers for temporarily storing transaction-related information passing through the router circuit between adapters on the PCI busses and/or between PCI adapters and the CPUs and system memory or other system devices. A buffer re-naming methodology is implemented to eliminate internal request/completion transaction information transfers between bridge buffers thereby increasing system performance.

Abstract: A packet memory system is provided. The packet memory system includes a memory cell array for storing a predefined number of packets. Each packet includes a predetermined number of segments. Each of the segments defines a starting point of a memory access. A packet decoder coupled to the memory cell array receives packet select inputs for selecting a packet. A segment decoder coupled to the memory cell array receives segment select inputs for selecting a segment. A data flow multiplexer is coupled to the memory cell array for transferring data between a data bus and the memory cell array. Command and mode registers receive command, read/write (R/W) and chip select (CS) inputs for opening a packet. Responsive to an opened packet, the packet select inputs provide a length for the memory access. Each of the segments has a preprogrammed length. Also each of the segments can be defined for a cache line.

Abstract: A data transmission system includes a sender and a receiver, both employing different clock rates and a data bus coupled between the sender and the receiver for transmitting signals therebetween. The receiver generates an enable signal from the receiver clock to control data transmission at the sender. The enable signal is a pulse generated at each rising edge of the receiver clock and corresponds to the data transfer rate of the receiver clock. A detector module, located at the sender, receives and captures the asynchronous enable signal and initiates transmission of one data byte for each pulse of the enable signal, thereby automatically adjusting the data transfer rate of the sender to the data transfer rate of the receiver.

Abstract: A memory controller design includes at least one memory instruction decoder de-embedded from a memory instruction processor wherein the memory instruction processor receives operations and logical address information from a host processor. The memory instruction processor converts the operations into generic memory instructions and translates the logical addresses into physical addresses. The memory instruction decoder further converts the generic memory instructions into memory specific control signals and converts the physical addresses into actual memory specific addresses. This design permits the memory instruction processor to be designed and finalized before an actual memory type is selected for system use at which time the less complex memory instruction decoder can be designed.

Abstract: A data processing system includes one or more processors connected to a common bus, one or more I/O controllers connected to the common bus and to one or more storage subsystems and one or more storage subsystems for storing data for use in the data processing system. One or more master controllers are included in each I/O controller for communicating with a memory controller referred to as a slave which controls data flow to and from a memory subsystem. The data bus between the I/O masters and the memory controller is a multi-drop operating synchronously on a two-by-two byte parallel interface.

Abstract: For an synchronous dynamic access memory ("S-DRAM") system including a memory assembly with multiple memory units, data access commands are placed on a command bus at specific times to facilitate gapless data bus operation. After receipt of a first memory access request, a first memory access command is issued on the command bus to exchange a first data string having a first length with a first one of the memory units. Subsequently, receipt occurs of a second memory access request is to exchange a second data string, of a second length, with a second one of the memory units. A determination is made of an earliest possible time for placement of a second memory access command upon the command bus; this considers various factors, such as the first length, data bus availability, command bus availability, and any predetermined delay in placement of the first data string onto the data bus. Accordingly, the second memory access command is placed upon the command bus at the determined time.