Patents by Inventor Adam Brand
Adam Brand has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11938097Abstract: A bottle comprises a body having an opening in an upper end for receiving fluid; a membrane provided to seal across the opening; and a receptacle sealingly secured to a surface of the membrane within the body. Separation of the membrane from the opening in the receptacle releases the receptacle such that the contents of the receptacle are released into the body.Type: GrantFiled: December 13, 2017Date of Patent: March 26, 2024Assignee: BOTTLE GO PTY LTDInventors: Brendan Paul James Richard Clark, Adam Brand, Michael Barton Longman, Edward Joseph Khoury
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Patent number: 11908691Abstract: A method of patterning a substrate. The method may include providing a surface feature on the substrate, the surface feature having a first dimension along a first direction within a substrate plane, and a second dimension along a second direction within the substrate plane, wherein the second direction is perpendicular to the first direction; and directing first ions in a first exposure to the surface feature along the first direction at a non-zero angle of incidence with respect to a perpendicular to the substrate plane, in a presence of a reactive ambient containing a reactive species; wherein the first exposure etches the surface feature along the first direction, wherein after the directing, the surface feature retains the second dimension along the second direction, and wherein the surface feature has a third dimension along the first direction different than the first dimension.Type: GrantFiled: September 23, 2022Date of Patent: February 20, 2024Assignee: Applied Materials, Inc.Inventors: Simon Ruffell, John Hautala, Adam Brand, Huixiong Dai
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LDMOS transistors including vertical gates with multiple dielectric sections, and associated methods
Patent number: 11699753Abstract: A lateral double-diffused metal-oxide-semiconductor transistor includes a silicon semiconductor structure and a vertical gate. The vertical gate include a (a) gate conductor extending from a first outer surface of the silicon semiconductor structure into the silicon semiconductor structure and (b) a gate dielectric layer including a least three dielectric sections. Each of the at least three dielectric sections separates the gate conductor from the silicon semiconductor structure by a respective separation distance, where each of the respective separation distances is different from each other of the respective separation distances.Type: GrantFiled: April 25, 2022Date of Patent: July 11, 2023Assignee: Maxim Integrated Products, Inc.Inventors: Tom K. Castro, Rajwinder Singh, Badredin Fatemizadeh, Adam Brand, John Xia, Chi-Nung Ni, Marco A. Zuniga -
Publication number: 20230020164Abstract: A method of patterning a substrate. The method may include providing a surface feature on the substrate, the surface feature having a first dimension along a first direction within a substrate plane, and a second dimension along a second direction within the substrate plane, wherein the second direction is perpendicular to the first direction; and directing first ions in a first exposure to the surface feature along the first direction at a non-zero angle of incidence with respect to a perpendicular to the substrate plane, in a presence of a reactive ambient containing a reactive species; wherein the first exposure etches the surface feature along the first direction, wherein after the directing, the surface feature retains the second dimension along the second direction, and wherein the surface feature has a third dimension along the first direction different than the first dimension.Type: ApplicationFiled: September 23, 2022Publication date: January 19, 2023Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Simon Ruffell, John Hautala, Adam Brand, Huixiong Dai
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Patent number: 11488823Abstract: A method of patterning a substrate. The method may include providing a surface feature on the substrate, the surface feature having a first dimension along a first direction within a substrate plane, and a second dimension along a second direction within the substrate plane, wherein the second direction is perpendicular to the first direction; and directing first ions in a first exposure to the surface feature along the first direction at a non-zero angle of incidence with respect to a perpendicular to the substrate plane, in a presence of a reactive ambient containing a reactive species; wherein the first exposure etches the surface feature along the first direction, wherein after the directing, the surface feature retains the second dimension along the second direction, and wherein the surface feature has a third dimension along the first direction different than the first dimension.Type: GrantFiled: February 8, 2021Date of Patent: November 1, 2022Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Simon Ruffell, John Hautala, Adam Brand, Huixiong Dai
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LDMOS TRANSISTORS INCLUDING VERTICAL GATES WITH MULTIPLE DIELECTRIC SECTIONS, AND ASSOCIATED METHODS
Publication number: 20220254922Abstract: A lateral double-diffused metal-oxide-semiconductor transistor includes a silicon semiconductor structure and a vertical gate. The vertical gate include a (a) gate conductor extending from a first outer surface of the silicon semiconductor structure into the silicon semiconductor structure and (b) a gate dielectric layer including a least three dielectric sections. Each of the at least three dielectric sections separates the gate conductor from the silicon semiconductor structure by a respective separation distance, where each of the respective separation distances is different from each other of the respective separation distances.Type: ApplicationFiled: April 25, 2022Publication date: August 11, 2022Inventors: Tom K. Castro, Rajwinder Singh, Badredin Fatemizadeh, Adam Brand, John Xia, Chi-Nung Ni, Marco A. Zuniga -
LDMOS transistors including vertical gates with multiple dielectric sections, and associated methods
Patent number: 11316044Abstract: A lateral double-diffused metal-oxide-semiconductor transistor includes a silicon semiconductor structure and a vertical gate. The vertical gate include a (a) gate conductor extending from a first outer surface of the silicon semiconductor structure into the silicon semiconductor structure and (b) a gate dielectric layer including a least three dielectric sections. Each of the at least three dielectric sections separates the gate conductor from the silicon semiconductor structure by a respective separation distance, where each of the respective separation distances is different from each other of the respective separation distances.Type: GrantFiled: June 5, 2018Date of Patent: April 26, 2022Assignee: Maxim Integrated Products, Inc.Inventors: Tom K. Castro, Rajwinder Singh, Badredin Fatemizadeh, Adam Brand, John Xia, Chi-Nung Ni, Marco A. Zuniga -
Patent number: 11043380Abstract: A method of patterning a substrate. The method may include providing a surface feature on the substrate, the surface feature having a first dimension along a first direction within a substrate plane, and a second dimension along a second direction within the substrate plane, wherein the second direction is perpendicular to the first direction; and directing first ions in a first exposure to the surface feature along the first direction at a non-zero angle of incidence with respect to a perpendicular to the substrate plane, in a presence of a reactive ambient containing a reactive species; wherein the first exposure etches the surface feature along the first direction, wherein after the directing, the surface feature retains the second dimension along the second direction, and wherein the surface feature has a third dimension along the first direction different than the first dimension.Type: GrantFiled: May 14, 2018Date of Patent: June 22, 2021Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Simon Ruffell, John Hautala, Adam Brand, Huixiong Dai
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Publication number: 20210166936Abstract: A method of patterning a substrate. The method may include providing a surface feature on the substrate, the surface feature having a first dimension along a first direction within a substrate plane, and a second dimension along a second direction within the substrate plane, wherein the second direction is perpendicular to the first direction; and directing first ions in a first exposure to the surface feature along the first direction at a non-zero angle of incidence with respect to a perpendicular to the substrate plane, in a presence of a reactive ambient containing a reactive species; wherein the first exposure etches the surface feature along the first direction, wherein after the directing, the surface feature retains the second dimension along the second direction, and wherein the surface feature has a third dimension along the first direction different than the first dimension.Type: ApplicationFiled: February 8, 2021Publication date: June 3, 2021Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Simon Ruffell, John Hautala, Adam Brand, Huixiong Dai
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Patent number: 10971368Abstract: A method of treating a substrate includes directing ions to the substrate along at least one non-zero angle with respect to a perpendicular to a substrate surface in a presence of a reactive ambient containing a reactive species where the substrate includes a surface feature. At least one surface of the surface feature is etched using the ions in combination with the reactive ambient at a first etch rate that is greater than a second etch rate when the ions are directed to the substrate without the reactive ambient and greater than a third etch rate when the reactive ambient is provided to the substrate without the ions.Type: GrantFiled: February 23, 2018Date of Patent: April 6, 2021Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Steven R. Sherman, Simon Ruffell, John Hautala, Adam Brand
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Publication number: 20200243659Abstract: A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor includes a silicon semiconductor structure and a vertical gate. The vertical gate includes (a) a first gate conductor and a second gate conductor each extending from a first outer surface of the silicon semiconductor structure into the silicon semiconductor structure in a thickness direction, (b) a first separation dielectric layer separating the first gate conductor from the second gate conductor within the vertical gate, and (c) a gate dielectric layer separating each of the first gate conductor and the second gate conductor from the silicon semiconductor structure.Type: ApplicationFiled: April 13, 2020Publication date: July 30, 2020Inventors: Tom K. Castro, Marco A. Zuniga, Badredin Fatemizadeh, Adam Brand, John Xia, Rajwinder Singh, Min Xu, Chi-Nung Ni
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Patent number: 10622452Abstract: A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor includes a silicon semiconductor structure and a vertical gate. The vertical gate includes (a) a first gate conductor and a second gate conductor each extending from a first outer surface of the silicon semiconductor structure into the silicon semiconductor structure in a thickness direction, (b) a first separation dielectric layer separating the first gate conductor from the second gate conductor within the vertical gate, and (c) a gate dielectric layer separating each of the first gate conductor and the second gate conductor from the silicon semiconductor structure.Type: GrantFiled: June 5, 2018Date of Patent: April 14, 2020Assignee: Maxim Integrated Products, Inc.Inventors: Tom K. Castro, Marco A. Zuniga, Badredin Fatemizadeh, Adam Brand, John Xia, Rajwinder Singh, Min Xu, Chi-Nung Ni
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Publication number: 20200078270Abstract: A bottle comprises a body having an opening in an upper end for receiving fluid; a membrane provided to seal across the opening; and a receptacle sealingly secured to a surface of the membrane within the body. Separation of the membrane from the opening in the receptacle releases the receptacle such that the contents of the receptacle are released into the body.Type: ApplicationFiled: December 13, 2017Publication date: March 12, 2020Inventors: Brendan Paul James Richard Clark, Adam Brand, Michael Barton Longman, Edward Joseph Khoury
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Patent number: 10573744Abstract: A dual-gate, self-aligned lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor includes a silicon semiconductor structure, a lateral gate including a first dielectric layer and a first conductive layer stacked on the silicon semiconductor structure in a thickness direction, and a vertical gate. The vertical gate includes a second dielectric layer and a second conductive layer disposed in a trench of the silicon semiconductor structure, the second dielectric layer defining an edge of the lateral gate in a lateral direction. A method for forming a dual-gate, self-aligned LDMOS transistor includes (a) forming a vertical gate of the LDMOS transistor in a trench of a silicon semiconductor structure and (b) defining a lateral edge of a lateral gate of the LDMOS transistor using the vertical gate.Type: GrantFiled: October 3, 2018Date of Patent: February 25, 2020Assignee: MAXIM INTEGRATED PRODUCTS, INC.Inventors: Marco A. Zuniga, Adam Brand, Tom K. Castro, Rajwinder Singh, Badredin Fatemizadeh
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Publication number: 20190371902Abstract: A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor includes a silicon semiconductor structure and a vertical gate. The vertical gate includes (a) a first gate conductor and a second gate conductor each extending from a first outer surface of the silicon semiconductor structure into the silicon semiconductor structure in a thickness direction, (b) a first separation dielectric layer separating the first gate conductor from the second gate conductor within the vertical gate, and (c) a gate dielectric layer separating each of the first gate conductor and the second gate conductor from the silicon semiconductor structure.Type: ApplicationFiled: June 5, 2018Publication date: December 5, 2019Inventors: Tom K. Castro, Marco A. Zuniga, Badredin Fatemizadeh, Adam Brand, John Xia, Rajwinder Singh, Min Xu, Chi-Nung Ni
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LDMOS TRANSISTORS INCLUDING VERTICAL GATES WITH MULTIPLE DIELECTRIC SECTIONS, AND ASSOCIATED METHODS
Publication number: 20180350980Abstract: A lateral double-diffused metal-oxide-semiconductor transistor includes a silicon semiconductor structure and a vertical gate. The vertical gate include a (a) gate conductor extending from a first outer surface of the silicon semiconductor structure into the silicon semiconductor structure and (b) a gate dielectric layer including a least three dielectric sections. Each of the at least three dielectric sections separates the gate conductor from the silicon semiconductor structure by a respective separation distance, where each of the respective separation distances is different from each other of the respective separation distances.Type: ApplicationFiled: June 5, 2018Publication date: December 6, 2018Inventors: Tom K. Castro, Rajwinder Singh, Badredin Fatemizadeh, Adam Brand, John Xia, Chi-Nung Ni, Marco A. Zuniga -
Patent number: 10134585Abstract: Surface pretreatment of SiGe or Ge surfaces prior to gate oxide deposition cleans the SiGe or Ge surface to provide a hydrogen terminated surface or a sulfur passivated (or S—H) surface. Atomic layer deposition (ALD) of a high-dielectric-constant oxide at a low temperature is conducted in the range of 25-200° C. to form an oxide layer. Annealing is conducted at an elevated temperature. A method for oxide deposition on a damage sensitive III-V semiconductor surface conducts in-situ cleaning of the surface with cyclic pulsing of hydrogen and TMA (trimethyl aluminum) at a low temperature in the range of 100-200° C. Atomic layer deposition (ALD) of a high-dielectric-constant oxide forms an oxide layer. Annealing is conducted at an elevated temperature. The annealing can create a silicon terminated interfaces.Type: GrantFiled: August 19, 2015Date of Patent: November 20, 2018Assignee: The Regents of the University of CaliforniaInventors: Kasra Sardashti, Tobin Kaufman-Osborn, Tyler Kent, Andrew Kummel, Shariq Siddiqui, Bhagawan Sahu, Adam Brand, Naomi Yoshida
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Publication number: 20180330944Abstract: A method of patterning a substrate. The method may include providing a surface feature on the substrate, the surface feature having a first dimension along a first direction within a substrate plane, and a second dimension along a second direction within the substrate plane, wherein the second direction is perpendicular to the first direction; and directing first ions in a first exposure to the surface feature along the first direction at a non-zero angle of incidence with respect to a perpendicular to the substrate plane, in a presence of a reactive ambient containing a reactive species; wherein the first exposure etches the surface feature along the first direction, wherein after the directing, the surface feature retains the second dimension along the second direction, and wherein the surface feature has a third dimension along the first direction different than the first dimension.Type: ApplicationFiled: May 14, 2018Publication date: November 15, 2018Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Simon Ruffell, John Hautala, Adam Brand, Huixiong Dai
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Patent number: 10109534Abstract: Methods for forming a multi-threshold voltage device on a substrate are provided herein. In some embodiments, the method of forming a multi-threshold voltage device may include (a) providing a substrate having a first layer disposed thereon, wherein the substrate comprises a first feature and a second feature disposed within the first layer; (b) depositing a blocking layer atop the substrate; (c) selectively removing a portion of the blocking layer from atop the substrate to expose the first feature; (d) selectively depositing a first work function layer atop the first feature; (e) removing a remainder of the blocking layer to expose the second feature; and (f) depositing a second work function layer atop the first work function layer and the second feature.Type: GrantFiled: February 20, 2015Date of Patent: October 23, 2018Assignee: APPLIED MATERIALS, INC.Inventors: Adam Brand, Naomi Yoshida, Seshadri Ganguli, David Thompson, Mei Chang
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Publication number: 20180182637Abstract: A method of treating a substrate includes directing ions to the substrate along at least one non-zero angle with respect to a perpendicular to a substrate surface in a presence of a reactive ambient containing a reactive species where the substrate includes a surface feature. At least one surface of the surface feature is etched using the ions in combination with the reactive ambient at a first etch rate that is greater than a second etch rate when the ions are directed to the substrate without the reactive ambient and greater than a third etch rate when the reactive ambient is provided to the substrate without the ions.Type: ApplicationFiled: February 23, 2018Publication date: June 28, 2018Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Steven R. Sherman, Simon Ruffell, John Hautala, Adam Brand