Patents by Inventor Adam Makosiej
Adam Makosiej has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170263308Abstract: SRAM memory bit cell comprising: a n-TFET and a p-TFET; a storage node formed by the connection of a first electrode of the n-TFET to a first electrode of the p-TFET (drains or sources); a control circuit able to apply supply voltages on second electrodes of the n-TFET and p-TFET (sources or drains); wherein the control circuit is configured to provide: during a retention mode, supply and bias voltages reverse biasing the n-TFET and p-TFET in a state wherein a conduction current is obtained by band-to-band tunneling in the n-TFET and p-TFET; during a writing of a bit, supply and bias voltages forward biasing the n-TFET and p-TFET and such that one of the n-TFET and p-TFET is in OFF state and that the other of the n-TFET and p-TFET is in ON state.Type: ApplicationFiled: March 8, 2017Publication date: September 14, 2017Applicant: Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Navneet GUPTA, Adam MAKOSIEJ, Costin ANGHEL, Amara AMARA
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Patent number: 9685222Abstract: Memory cell of the SRAM type, including storage transistors forming a memory point for storing a bit and a read port having at least one MOS transistor, a TFET transistor, a power terminal and a read bit line whereof a potential is designed to vary depending on the value of the stored bit, and such that: the gate of the MOS transistor is connected to the memory point, and the gate of the TFET transistor is able to receive a read command signal; a first electrode of the MOS transistor is connected to the power supply terminal; a second electrode of the MOS transistor is connected to a first electrode of the TFET transistor; a second electrode of the TFET transistor is connected to the read bit line.Type: GrantFiled: October 14, 2015Date of Patent: June 20, 2017Assignee: Commissariat à l'énergie atomique et aux énergies alternativesInventors: Olivier Thomas, Costin Anghel, Adam Makosiej
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Patent number: 9679649Abstract: A content addressable memory having at least one CAM cell including first and second inverters cross-coupled between first and second storage nodes; a first transistor coupling the first storage node to a bitline, the first transistor being controlled by a first control signal; a second transistor coupling the second storage node to the bitline, the second transistor being controlled by a second control signal; and a control circuit adapted to perform a CAM read operation by pre-charging the bitline to a first voltage level, and then selectively activating either the first or second transistor based on a bit of input data.Type: GrantFiled: November 3, 2016Date of Patent: June 13, 2017Assignee: Commissariat à l'Énergie Atomique et aux Énergies AlternativesInventors: Navneet Gupta, Adam Makosiej, Costin Anghel, Amara Amara, Olivier Thomas
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Publication number: 20170133092Abstract: A content addressable memory having at least one CAM cell including first and second inverters cross-coupled between first and second storage nodes; a first transistor coupling the first storage node to a bitline, the first transistor being controlled by a first control signal; a second transistor coupling the second storage node to the bitline, the second transistor being controlled by a second control signal; and a control circuit adapted to perform a CAM read operation by pre-charging the bitline to a first voltage level, and then selectively activating either the first or second transistor based on a bit of input data.Type: ApplicationFiled: November 3, 2016Publication date: May 11, 2017Applicant: Commissariat à l'Énergie Atomique et aux Énergies AlternativesInventors: Navneet Gupta, Adam Makosiej, Costin Anghel, Amara Amara, Olivier Thomas
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Publication number: 20170110179Abstract: Memory cell of the SRAM type, including storage transistors forming a memory point for storing a bit and a read port having at least one MOS transistor, a TFET transistor, a power terminal and a read bit line whereof a potential is designed to vary depending on value of the stored bit, and such that: the gate of the MOS transistor is connected to the memory point, and the gate of the TFET transistor is able to receive a read command signal; a first electrode of the MOS transistor is connected to the power supply terminal; a second electrode of the MOS transistor is connected to a first electrode of the TFET transistor; a second electrode of the TFET transistor is connected to the read bit line.Type: ApplicationFiled: October 14, 2015Publication date: April 20, 2017Applicant: Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Olivier THOMAS, Costin ANGHEL, Adam MAKOSIEJ
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Patent number: 9542996Abstract: A memory device includes a matrix of several columns of SRAM memory cells each including transistors forming a memory point, a read port and a write port, and such that the transistors of the read port and/or the P-type transistors include a second well with a conductivity type opposite that of a first well of the other transistors. The memory device also includes a polarization unit for the second wells, able to select and apply polarization potentials on the second wells, including a memory circuit of the polarization states of the second wells for each column or group of columns and a selection circuit applying a polarization potential on the second wells according to one of the values received as input, as a function of the stored polarization state associated with the column or group of columns.Type: GrantFiled: September 10, 2015Date of Patent: January 10, 2017Assignee: Commissariat à l'énergie atomique et aux énergies alternativesInventors: Olivier Thomas, Bastien Giraud, Adam Makosiej
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Patent number: 9508434Abstract: A non-volatile memory including a plurality of elementary cells, each cell including: a first programmable-resistance storage element connected between first and second nodes of the cell; a first access transistor coupling the second node to a third node of the cell; and a second access transistor coupling the second node to a fourth node of the cell.Type: GrantFiled: July 23, 2015Date of Patent: November 29, 2016Assignee: Commissariat à l'Energie Atomique et aux Energies AlternativesInventors: Thomas-Medhi Benoist, Haithem Ayari, Bastien Giraud, Adam Makosiej, Yves Maneglia, Santhosh Onkaraiah, Jean-Michel Portal, Olivier Thomas
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Publication number: 20160078924Abstract: A memory device includes a matrix of several columns of SRAM memory cells each including transistors forming a memory point, a read port and a write port, and such that the transistors of the read port and/or the P-type transistors include a second well with a conductivity type opposite that of a first well of the other transistors. The memory device also includes a polarization unit for the second wells, able to select and apply polarization potentials on the second wells, including a memory circuit of the polarization states of the second wells for each column or group of columns and a selection circuit applying a polarization potential on the second wells according to one of the values received as input, as a function of the stored polarization state associated with the column or group of columns.Type: ApplicationFiled: September 10, 2015Publication date: March 17, 2016Applicant: Commissariat a L'Energie Atomique et aux Energies AlternativesInventors: Olivier THOMAS, Bastien GIRAUD, Adam MAKOSIEJ
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Patent number: 9252269Abstract: A tunnel effect transistor includes a channel made of an intrinsic semiconductor material; source and drain extension regions on either side of the channel, the source extension region being made of a semiconductor material doped according to a first type of doping P or N and the drain extension region being made of a semiconductor material doped according to a second type of doping opposite to said first type of doping; source and drain conductive regions respectively in contact with the source and drain extension regions; a gate structure including a gate dielectric layer in contact with the channel and a gate area arranged such that the gate dielectric layer is arranged between the gate area and the channel; and an area doped according to the first type of doping inserted between the channel and the drain extension region.Type: GrantFiled: March 6, 2014Date of Patent: February 2, 2016Assignee: Commissariat à l'ènergie atomique et aux ènergies alernativesInventors: Costin Anghel, Cyrille Le Royer, Adam Makosiej
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Publication number: 20160027509Abstract: A non-volatile memory including a plurality of elementary cells, each cell including: a first programmable-resistance storage element connected between first and second nodes of the cell; a first access transistor coupling the second node to a third node of the cell; and a second access transistor coupling the second node to a fourth node of the cell.Type: ApplicationFiled: July 23, 2015Publication date: January 28, 2016Inventors: Thomas-Medhi BENOIST, Haithem AYARI, Bastien GIRAUD, Adam MAKOSIEJ, Yves MANEGLIA, Santhosh ONKARAIAH, Jean-Michel PORTAL, Olivier THOMAS
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Patent number: 9099993Abstract: CMOS integrated circuits with very low consumption when idle, and notably the SRAM volatile memories, are provided. The inverters of the circuit are made up of an NMOS transistor and a PMOS transistor. A bias circuit applies a first rear bias voltage NBIAS to the wells of the NMOS transistors and a second rear bias voltage PBIAS to the wells of the PMOS transistors. The bias circuit comprises: a detection array made up of many inverters in parallel, having a common output supplying a logic signal whose value depends on the rear bias voltages applied to the array, a circuit for producing incrementation or decrementation pulses, controlled by the output of the detection array, and an integration circuit linked to the pulse-producing circuit, for producing and varying, progressively by increments in response to these pulses, a bias voltage PBIAS and a bias voltage NBIAS.Type: GrantFiled: October 18, 2012Date of Patent: August 4, 2015Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Olivier Thomas, Adam Makosiej, Andrei Vladimirescu
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Publication number: 20140334226Abstract: CMOS integrated circuits with very low consumption when idle, and notably the SRAM volatile memories, are provided. The inverters of the circuit are made up of an NMOS transistor and a PMOS transistor. A bias circuit applies a first rear bias voltage NBIAS to the wells of the NMOS transistors and a second rear bias voltage PBIAS to the wells of the PMOS transistors. The bias circuit comprises: a detection array made up of many inverters in parallel, having a common output supplying a logic signal whose value depends on the rear bias voltages applied to the array, a circuit for producing incrementation or decrementation pulses, controlled by the output of the detection array, and an integration circuit linked to the pulse-producing circuit, for producing and varying, progressively by increments in response to these pulses, a bias voltage PBIAS and a bias voltage NBIAS.Type: ApplicationFiled: October 18, 2012Publication date: November 13, 2014Inventors: Olivier Thomas, Adam Makosiej, Andrei Vladimirescu
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Publication number: 20140252407Abstract: A tunnel effect transistor includes a channel made of an intrinsic semiconductor material; source and drain extension regions on either side of the channel, the source extension region being made of a semiconductor material doped according to a first type of doping P or N and the drain extension region being made of a semiconductor material doped according to a second type of doping opposite to said first type of doping; source and drain conductive regions respectively in contact with the source and drain extension regions; a gate structure including a gate dielectric layer in contact with the channel and a gate area arranged such that the gate dielectric layer is arranged between the gate area and the channel; and an area doped according to the first type of doping inserted between the channel and the drain extension region.Type: ApplicationFiled: March 6, 2014Publication date: September 11, 2014Inventors: Costin Anghel, Cyrille Le Royer, Adam Makosiej