Abstract: The present disclosure relates to a precharge circuitry for bit lines of an array of memory cells, the precharge circuitry comprising a precharge and limiting unit configured to precharge a first bit line and a second bit line, the precharge and limiting unit further configured to limit a first bit line precharge level of the first bit line and a second bit line precharge level of the second bit line during a precharge cycle of a read and/or write operation of any of the memory cells, wherein the precharge and limiting unit is configured to limit the first bit line precharge level and the second bit line precharge level in a single precharge cycle, preferably without substantial delay.

Abstract: A memory device including a matrix of memory cells including FET transistors including back-bias elements, of which at least one column forms back-bias bits; a back-bias circuit outputting voltages dependent on back-bias bits; first and second coupling elements, coupling memory dots of back-bias bits with the back-bias circuit, and the back-bias circuit with the back-bias elements of the cells of the matrix; wherein the device forms a 3D circuit including first and second active layers between which several interconnection layers are stacked; the first and/or the second coupling elements include metallic portions of one of the interconnection layers.

Abstract: A 3D microelectronic device is provided with several superimposed layers of components, with an upper layer including one or several memory cells having a SRAM structure and provided with a rear biasing electrode. The biasing of the rear biasing electrode is modified to switch the memory cells from a ROM operating mode to a SRAM operating mode.

Abstract: A memory circuit including a plurality of elementary cells arranged in a plurality of arrays, each including a plurality of rows and a plurality of columns, and wherein: the elementary cells having the same coordinates in the different arrays share a same first conductive track; and in each array, the elementary cells of a same row of the array share a same second conductive track and a same third conductive track.

Abstract: Memory device provided with a set of memory cells having a first inverter and a second inverter each connected to a supply line from a first supply line and a second supply line, the memory device being provided with a circuit element configured for: during a start-up phase consecutive to a powering on, applying a first pair of potentials, respectively to the first supply line and the second supply line, in order to pre-load a logic data to some cells depending on the manner in which said cells are respectively connected to said supply lines, then during a second phase, applying a second pair of potentials respectively to said first supply line and the second supply line, so as to symmetrically supply the inverters of each cell.

Abstract: Memory circuit for implementing logic operations and provided with memory cells, in particular of structure 6T, with a control circuit configured to activate the first access transistors or the second access transistors of at least two cells of the same given column and for detecting from a low- or high-voltage power supply line, from said given column, separate from the bit lines, a signal representative of the result of a logic operation having for operands data stored in said at least two cells.

Abstract: Circuit for triggering the end of a read operation, for a SRAM memory device, comprising: a plurality of pairs of transistors connected to a bit line and an additional bit line, the transistors each having a source connected to a node, the node and the bit lines being, prior to the activation of said given word line, respectively pre-charged via the pre-charging means, then, when said word line is activated, at least the bit lines are disconnected from the pre-charging means, in such a way as to modify the conduction state of certain transistors and consequently cause a variation in the potential of said node until reaching a determined threshold potential that triggers the emission of an end-of-phase signal.

Abstract: A PVT detection circuit including: first and second transistors of a first conduction type each having its control node coupled to a control line, the first and second transistors being configured such that the variations in their threshold voltages as a function of temperature and/or process are different from each other; and an amplifier coupled to a second main conducting node of each of the first and second transistors and configured to amplify a difference in the currents conducted by the first and second transistors in order to generate an output signal.

Abstract: A 3D-RAM memory comprising: several memory cell arrays distributed in several superimposed memory layers; a word line driver; a row decoder coupled to the word line driver; wherein the row decoder and the word line driver are arranged in a layer of command electronics which is separate from the memory layers, and wherein, in each of the memory layers, each of the word lines is connected to an output of an electronic selection device arranged in the memory layer, a data input of which is connected to the word line driver, a command input of which is connected to the row decoder, and which is configured to let a signal of access to the transistors pass or not depending on the value of a received command signal.

Abstract: Memory circuit for implementing logic operations and provided with memory cells, in particular of structure 6T, with a control circuit configured to activate the first access transistors or the second access transistors of at least two cells of the same given column and for detecting from a low- or high-voltage power supply line, from said given column, separate from the bit lines, a signal representative of the result of a logic operation having for operands data stored in said at least two cells.

Abstract: 3D microelectronic device provided with several superimposed layers of components with an upper layer comprising one or several memory cells having a SRAM structure and provided with a rear biasing electrode of which the biasing is modified to switch the cells from a ROM mode operating mode to a SRAM mode operating mode (FIG. 2).

Abstract: Memory device provided with a set of memory cells having a first inverter and a second inverter each connected to a supply line from a first supply line and a second supply line, the memory device being provided with a circuit element configured for: during a start-up phase consecutive to a powering on, applying a first pair of potentials, respectively to the first supply line and the second supply line, in order to pre-load a logic data to some cells depending on the manner in which said cells are respectively connected to said supply lines, then during a second phase, applying a second pair of potentials respectively to said first supply line and the second supply line, so as to symmetrically supply the inverters of each cell.

Abstract: Circuit for triggering the end of a read operation, for a SRAM memory device, comprising: a plurality of pairs of transistors connected to a bit line and an additional bit line, the transistors each having a source connected to a node, the node and the bit lines being, prior to the activation of said given word line, respectively pre-charged via the pre-charging means, then, when said word line is activated, at least the bit lines are disconnected from the pre-charging means, in such a way as to modify the conduction state of certain transistors and consequently cause a variation in the potential of said node until reaching a determined threshold potential that triggers the emission of an end-of-phase signal.

Abstract: A PVT detection circuit including: first and second transistors of a first conduction type each having its control node coupled to a control line, the first and second transistors being configured such that the variations in their threshold voltages as a function of temperature and/or process are different from each other; and an amplifier coupled to a second main conducting node of each of the first and second transistors and configured to amplify a difference in the currents conducted by the first and second transistors in order to generate an output signal.

Abstract: A memory circuit including a plurality of elementary cells arranged in a plurality of arrays, each including a plurality of rows and a plurality of columns, and wherein: the elementary cells having the same coordinates in the different arrays share a same first conductive track; and in each array, the elementary cells of a same row of the array share a same second conductive track and a same third conductive track.

Abstract: A CAM memory cell including: a latch including N first TFETs serially connected one to the other between two supply electric potentials such that each source and drain of each first TFETs is connected either to one supply electric potentials or to the source or drain of another first TFETs, and wherein one electric potentials is applied on the gate of each first TFETs which are in reverse bias VDS and forward bias VGS, with N?2; an output block connected to N?1 storage nodes formed at connection points between the first TFETs, and configured to read a data stored in the storage nodes and/or to output a value representative of a matching or mismatching between a search data and the stored data; a write block configured to apply a data to be stored in the storage nodes.

Abstract: Tri-state inverter includes a n-TFET and a p-TFET, the drain of the n-TFET being connected to the drain of the p-TFET and to an output of the tri-state inverter, the gates of the n-TFET and p-TFET being connected to an input of the tri-state inverter, and a control circuit able to apply a first control voltage on the source of the n-TFET and a second control voltage on the source of the p-TFET, the values of the first and second control voltages being positive or zero, wherein, when the tri-state inverter is intended to work as an inverter, the value of the first control voltage is lower than the value of the second control voltage, and when the tri-state inverter is intended to be tri-stated, the value of the first control voltage is higher than the value of the second control voltage.

Abstract: Memory latch comprising: a TFET; a capacitor; a storage node formed by the connection of a first terminal of the capacitor to a first electrode of the TFET; a control circuit configured to supply a first electric potential on a second terminal of the capacitor, a second electric potential on the gate of the TFET and a third electric potential on a second electrode of the TFET, such that: when the stored potential is low, the TFET is reverse biased with a conduction current obtained by band-to-band tunneling with a value higher than a capacitor leakage current; when the stored potential is high, the TFET is reverse biased with an OFF state current value less than the capacitor leakage current.

Abstract: A SRAM memory bit cell is provided that includes a n-TFET and a p-TFET; a storage node formed by the connection of a first electrode of the n-TFET to a first electrode of the p-TFET (drains or sources); and a control circuit able to apply supply voltages on second electrodes of the n-TFET and p-TFET (sources or drains). The control circuit is configured to provide, during a retention mode, supply and bias voltages reverse biasing the n-TFET and p-TFET in a state wherein a conduction current is obtained by band-to-band tunneling in the n-TFET and p TFET. The control circuit is further configured to provide, during a writing of a bit, supply and bias voltages forward biasing the n-TFET and p-TFET and such that one of the n-TFET and p-TFET is in OFF state and that the other of the n-TFET and p-TFET is in ON state.

Abstract: Tri-state inverter comprising: a n-TFET and a p-TFET, the drain of the n-TFET being connected to the drain of the p-TFET and to an output of the tri-state inverter, the gates of the n-TFET and p-TFET being connected to an input of the tri-state inverter; a control circuit able to apply a first control voltage on the source of the n-TFET and a second control voltage on the source of the p-TFET, the values of the first and second control voltages being positive or zero; and wherein, when the tri-state inverter is intended to work as an inverter, the value of the first control voltage is lower than the value of the second control voltage, and when the tri-state inverter is intended to be tri-stated, the value of the first control voltage is higher than the value of the second control voltage.