Abstract: A semiconductor structure includes a Group III-nitride semiconductor layer, a protective layer on the semiconductor layer, a distribution of implanted dopants within the semiconductor layer, and an ohmic contact extending through the protective layer to the semiconductor layer.

Abstract: A semiconductor structure includes a Group III-nitride semiconductor layer, a protective layer on the semiconductor layer, a distribution of implanted dopants within the semiconductor layer, and an ohmic contact extending through the protective layer to the semiconductor layer.

Abstract: Methods of forming a semiconductor device include forming a protective layer on a semiconductor layer, implanting ions having a first conductivity type through the protective layer into the semiconductor layer to form an implanted region of the semiconductor layer, and annealing the semiconductor layer and the protective layer to activate the implanted ions. An opening is formed in the protective layer to expose the implanted region of the semiconductor layer, and an electrode is formed in the opening. A semiconductor structure includes a Group III-nitride semiconductor layer, a protective layer on the semiconductor layer, a distribution of implanted dopants within the semiconductor layer, and an ohmic contact extending through the protective layer to the semiconductor layer.

Abstract: Transistors and/or methods of fabricating transistors that include a source contact, drain contact and gate contact are provided. In some embodiments, a channel region is provided between the source and drain contacts and at least a portion of the channel regions includes a hybrid layer comprising semiconductor material. In particular embodiments of the present invention, the transistor is a current aperture transistor. The channel region may include pendeo-epitaxial layers or epitaxial laterally overgrown layers. Transistors and methods of fabricating current aperture transistors that include a trench that extends through the channel and barrier layers and includes semiconductor material therein are also provided.

Abstract: High electron mobility transistors are provided that include a non-uniform aluminum concentration AlGaN based cap layer having a high aluminum concentration adjacent a surface of the cap layer that is remote from the barrier layer on which the cap layer is provided. High electron mobility transistors are provided that include a cap layer having a doped region adjacent a surface of the cap layer that is remote from the barrier layer on which the cap layer is provided. Graphitic BN passivation structures for wide bandgap semiconductor devices are provided. SiC passivation structures for Group III-nitride semiconductor devices are provided. Oxygen anneals of passivation structures are also provided. Ohmic contacts without a recess are also provided.

Abstract: Methods of forming a semiconductor device include forming a protective layer on a semiconductor layer, implanting ions having a first conductivity type through the protective layer into the semiconductor layer to form an implanted region of the semiconductor layer, and annealing the semiconductor layer and the protective layer to activate the implanted ions. An opening is formed in the protective layer to expose the implanted region of the semiconductor layer, and an electrode is formed in the opening. A semiconductor structure includes a Group III-nitride semiconductor layer, a protective layer on the semiconductor layer, a distribution of implanted dopants within the semiconductor layer, and an ohmic contact extending through the protective layer to the semiconductor layer.

Abstract: A solid state light emitting device comprising an emitter structure having an active region of semiconductor material and a pair of oppositely doped layers of semiconductor material on opposite sides of the active region. The active region emits light at a predetermined wavelength in response to an electrical bias across the doped layers. An absorption layer of semiconductor material is included that is integral to said emitter structure and doped with at least one rare earth or transition element. The absorption layer absorbs at least some of the light emitted from the active region and re-emits at least one different wavelength of light. A substrate is included with the emitter structure and absorption layer disposed on the substrate.

Abstract: A gas driven apparatus and method that can be useful for growing crystalline materials are provided. The gas driven rotation apparatus can include one or more rotatable substrate support members, each of which can be configured to support at least one substrate having a growth surface oriented in a downwardly facing position. The gas driven rotation apparatus can further include one or more drive gas channels adapted to direct the flow of a drive gas to rotate the substrate support member. One or more substrates can be positioned in the apparatus so that the growth surface of each substrate is downwardly oriented. A drive gas can flow through the drive gas channel to rotate the substrate. During rotation, reactant gases can be introduced to contact the downwardly facing growth surface, and epitaxial layers of a crystalline material can thereby be grown in a downward direction.

Abstract: A solid state light emitting device according to the present invention comprises an emitter structure having an active region of semiconductor material and a pair of oppositely doped layers of semiconductor material on opposite sides of said active region. The active region emits light at a first wavelength in response to an electrical bias across said doped layers. A quantum well structure is included that is integral to the emitter structure and has a plurality of layers having a composition and thickness such that the quantum well structure absorbs at least some of the light emitted from the active region and re-emits light of at least one different wavelength of light from said first wavelength.

Abstract: Semi-insulating Group III nitride layers and methods of fabricating semi-insulating Group III nitride layers include doping a Group III nitride layer with a shallow level p-type dopant and doping the Group III nitride layer with a deep level dopant, such as a deep level transition metal dopant. Such layers and/or method may also include doping a Group III nitride layer with a shallow level dopant having a concentration of less than about 1×1017 cm?3 and doping the Group III nitride layer with a deep level transition metal dopant. The concentration of the deep level transition metal dopant is greater than a concentration of the shallow level p-type dopant.

Abstract: Group III nitride semiconductor device structures are provided that include a silicon carbide (SiC) substrate and a Group III nitride epitaxial layer above the SiC substrate. The Group III nitride epitaxial layer has a dislocation density of less than about 4×108 cm?2 and/or an isolation voltage of at least about 50V.

Abstract: A monolithic electronic device includes a first nitride epitaxial structure including a plurality of nitride epitaxial layers. The plurality of nitride epitaxial layers include at least one common nitride epitaxial layer. A second nitride epitaxial structure is on the common nitride epitaxial layer of the first nitride epitaxial structure. A first plurality of electrical contacts is on the first epitaxial nitride structure and defines a first electronic device in the first nitride epitaxial structure. A second plurality of electrical contacts is on the first epitaxial nitride structure and defines a second electronic device in the second nitride epitaxial structure. A monolithic electronic device includes a bulk semi-insulating silicon carbide substrate having implanted source and drain regions and an implanted channel region between the source and drain regions, and a nitride epitaxial structure on the surface of the silicon carbide substrate. Corresponding methods are also disclosed.

Abstract: A semiconductor structure is disclosed that includes a silicon carbide wafer having a diameter of at least 100 mm with a Group III nitride heterostructure on the wafer that exhibits high uniformity in a number of characteristics. These include: a standard deviation in sheet resistivity across the wafer less than three percent; a standard deviation in electron mobility across the wafer of less than 1 percent; a standard deviation in carrier density across the wafer of no more than about 3.3 percent; and a standard deviation in conductivity across the wafer of about 2.5 percent.

Abstract: A heterojunction transistor may include a channel layer comprising a Group III nitride, a barrier layer comprising a Group III nitride on the channel layer, and an energy barrier comprising a layer of a Group III nitride including indium on the channel layer such that the channel layer is between the barrier layer and the energy barrier. The barrier layer may have a bandgap greater than a bandgap of the channel layer, and a concentration of indium (In) in the energy barrier may be greater than a concentration of indium (In) in the channel layer. Related methods are also discussed.

Abstract: Binary Group III-nitride high electron mobility transistors (HEMTs) and methods of fabricating binary Group III-nitride HEMTs are provided. In some embodiments, the binary Group III-nitride HEMTs include a first binary Group III-nitride barrier layer, a binary Group III-nitride channel layer on the first barrier layer; and a second binary Group III-nitride barrier layer on the channel layer. In some embodiments, the binary Group III-nitride HEMTs include a first AIN barrier layer, a GaN channel layer and a second AlN barrier layer.

Abstract: Aluminum free high electron mobility transistors (HEMTs) and methods of fabricating aluminum free HEMTs are provided. In some embodiments, the aluminum free HEMTs include an aluminum free Group III-nitride barrier layer, an aluminum free Group III-nitride channel layer on the barrier layer and an aluminum free Group III-nitride cap layer on the channel layer.

Abstract: Semiconductor device structures and methods of fabricating semiconductor devices structures are provided that include a semi-insulating or insulating GaN epitaxial layer on a conductive semiconductor substrate and/or a conductive layer. The semi-insulating or insulating GaN epitaxial layer has a thickness of at least about 4 ?m. GaN semiconductor device structures and methods of fabricating GaN semiconductor device structures are also provided that include an electrically conductive SiC substrate and an insulating or semi-insulating GaN epitaxial layer on the conductive SiC substrate. The GaN epitaxial layer has a thickness of at least about 4 ?m.

Abstract: Group III-Nitride semiconductor device structures and methods of fabricating Group III-Nitride structures are provided that include an electrically conductive Group III-Nitride substrate, such as a GaN substrate, and a semi-insulating or insulating Group III-Nitride epitaxial layer, such as a GaN epitaxial layer, on the electrically conductive Group III-Nitride substrate. The Group III-Nitride epitaxial layer has a lattice constant that is and a composition that may be substantially the same as a composition and a lattice constant of the Group III-Nitride substrate.

Abstract: Transistors and/or methods of fabricating transistors that include a source contact, drain contact and gate contact are provided. In some embodiments, a channel region is provided between the source and drain contacts and at least a portion of the channel regions includes a hybrid layer comprising semiconductor material. In particular embodiments of the present invention, the transistor is a current aperture transistor. The channel region may include pendeo-epitaxial layers or epitaxial laterally overgrown layers. Transistors and methods of fabricating current aperture transistors that include a trench that extends through the channel and barrier layers and includes semiconductor material therein are also provided.

Abstract: Group III Nitride based field effect transistor (FETS) are provided having a power degradation of less than about 3.0 dB when operated at a drain-to-source voltage (VDS) of about 56 volts, a gate to source voltage (Vgs) of from about ?8 to about ?14 volts and a temperature of about 140 ° C. for at least about 10 hours.