Patents by Inventor Adarsh RAJASHEKHAR

Adarsh RAJASHEKHAR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210036019
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and a memory stack structure extending through the alternating stack. The memory stack structure includes a vertical semiconductor channel, a vertical stack of majority germanium layers each containing at least 51 atomic percent germanium, and a vertical stack of ferroelectric dielectric layers.
    Type: Application
    Filed: June 24, 2020
    Publication date: February 4, 2021
    Inventors: Rahul Sharangpani, Adarsh Rajashekhar, Raghuveer S. Makala, Fei Zhou, Seung-Yeul Yang
  • Publication number: 20210036018
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack. Each of the memory stack structures includes a vertical stack of single crystalline ferroelectric dielectric layers and a respective vertical semiconductor channel.
    Type: Application
    Filed: August 2, 2019
    Publication date: February 4, 2021
    Inventors: Adarsh Rajashekhar, Fei Zhou, Rahul Sharangpani, Raghuveer S. Makala
  • Publication number: 20200395380
    Abstract: A semiconductor structure includes a memory die bonded to a support die. The memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate including a single crystalline substrate semiconductor material, and memory stack structures extending through the alternating stack and containing a respective memory film and a respective vertical semiconductor channel including a single crystalline channel semiconductor material. The support die contains a peripheral circuitry.
    Type: Application
    Filed: August 27, 2020
    Publication date: December 17, 2020
    Inventors: Adarsh Rajashekhar, Raghuveer S. Makala, Fei Zhou, Rahul Sharangpani
  • Patent number: 10868025
    Abstract: In-process source-level material layers including a source-level sacrificial layer are formed over a substrate. An alternating stack of insulating layers and sacrificial material layers is formed over the in-process source-level material layers. A memory opening is formed through the alternating stack, and is filled with a memory film and a sacrificial opening fill structure. The source-level sacrificial layer is replaced with a source contact layer including a doped polycrystalline semiconductor material. The source contact layer can be formed by diffusing a metal in a metallic catalyst material through a semiconductor fill material layer that fills a source cavity formed by removal of the source-level sacrificial layer. The sacrificial opening fill structure is replaced with a vertical semiconductor channel, which can be formed with large grains due to large crystal sizes in the source contact layer. The sacrificial material layers are replaced with electrically conductive layers.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: December 15, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Fei Zhou, Adarsh Rajashekhar, Rahul Sharangpani, Raghuveer S. Makala
  • Publication number: 20200335516
    Abstract: A semiconductor structure includes a memory die bonded to a support die. The memory die includes an alternating stack of insulating layers and electrically conductive layers located over a first single crystalline semiconductor layer, and memory stack structures extending through the alternating stack and containing respective memory film and a respective vertical semiconductor channel including a single crystalline channel semiconductor material. The support die includes a peripheral circuitry.
    Type: Application
    Filed: June 30, 2020
    Publication date: October 22, 2020
    Inventors: Adarsh RAJASHEKHAR, Raghuveer S. MAKALA, Fei ZHOU
  • Publication number: 20200335487
    Abstract: A semiconductor structure includes a memory die bonded to a support die. The memory die includes an alternating stack of insulating layers and electrically conductive layers located over a first single crystalline semiconductor layer, and memory stack structures extending through the alternating stack and containing respective memory film and a respective vertical semiconductor channel including a single crystalline channel semiconductor material. The support die includes a peripheral circuitry.
    Type: Application
    Filed: June 30, 2020
    Publication date: October 22, 2020
    Inventors: Adarsh RAJASHEKHAR, Raghuveer S. MAKALA, Fei ZHOU
  • Patent number: 10804291
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a single crystalline semiconductor layer, a single crystal epitaxial source semiconductor layer located between the single crystalline semiconductor layer and the alternating stack and epitaxially aligned to the single crystalline semiconductor layer, and a memory stack structure vertically extending through the alternating stack and containing a memory film and an epitaxial vertical semiconductor channel including a single crystal semiconductor material that is epitaxially aligned to the epitaxial source semiconductor layer at an interface.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: October 13, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Adarsh Rajashekhar, Fei Zhou, Rahul Sharangpani, Raghuveer S. Makala
  • Patent number: 10797060
    Abstract: Three-dimensional memory devices include structures that induce a vertical tensile stress in vertical semiconductor channels to enhance charge carrier mobility. Vertical tensile stress may be induced by a laterally compressive stress applied by stressor pillar structure. The stressor pillar structures can include a stressor material such as a dielectric metal oxide material, silicon nitride, thermal silicon oxide or a semiconductor material having a greater lattice constant than that of the channel. Vertical tensile stress may be induced by a compressive stress applied by electrically conductive layers that laterally surround the vertical semiconductor channel, or by a stress memorization technique that captures a compressive stress from sacrificial material layers. Vertical tensile stress can be generated by a source-level pinning layer that prevents vertical expansion of the vertical semiconductor channel.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: October 6, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Raghuveer S. Makala, Adarsh Rajashekhar, Fei Zhou, Srikanth Ranganathan, Akio Nishida, Toshihiro Iizuka
  • Patent number: 10797061
    Abstract: Three-dimensional memory devices include structures that induce a vertical tensile stress in vertical semiconductor channels to enhance charge carrier mobility. Vertical tensile stress may be induced by a laterally compressive stress applied by stressor pillar structure. The stressor pillar structures can include a stressor material such as a dielectric metal oxide material, silicon nitride, thermal silicon oxide or a semiconductor material having a greater lattice constant than that of the channel. Vertical tensile stress may be induced by a compressive stress applied by electrically conductive layers that laterally surround the vertical semiconductor channel, or by a stress memorization technique that captures a compressive stress from sacrificial material layers. Vertical tensile stress can be generated by a source-level pinning layer that prevents vertical expansion of the vertical semiconductor channel.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: October 6, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Akio Nishida, Toshihiro Iizuka, Rahul Sharangpani, Raghuveer S. Makala, Adarsh Rajashekhar, Fei Zhou, Srikanth Ranganathan
  • Patent number: 10790300
    Abstract: A semiconductor structure includes a memory die bonded to a support die. The memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate including a single crystalline substrate semiconductor material, and memory stack structures extending through the alternating stack and containing a respective memory film and a respective vertical semiconductor channel including a single crystalline channel semiconductor material. The support die contains a peripheral circuitry.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: September 29, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Adarsh Rajashekhar, Raghuveer S. Makala, Fei Zhou, Rahul Sharangpani
  • Publication number: 20200279862
    Abstract: A semiconductor structure includes a memory die bonded to a support die. The memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate including a single crystalline substrate semiconductor material, and memory stack structures extending through the alternating stack and containing a respective memory film and a respective vertical semiconductor channel including a single crystalline channel semiconductor material. The support die contains a peripheral circuitry.
    Type: Application
    Filed: March 1, 2019
    Publication date: September 3, 2020
    Inventors: Adarsh Rajashekhar, Raghuveer S. Makala, Fei Zhou, Rahul Sharangpani
  • Patent number: 10756110
    Abstract: Memory pillar structures extending through an alternating stack of insulating layers and word-line-level electrically conductive layers are formed over a substrate. Each of the memory pillar structures includes a vertical semiconductor channel and a memory film. Each of the memory pillar structures protrudes above an insulating cap layer located above the alternating stack to provide an inter-pillar gap region that laterally extends between laterally-neighboring pairs of the memory pillar structures. A metal-nucleating material having a physically exposed metal-nucleating surface is formed at a bottom of the inter-pillar gap region without covering upper portions of sidewalls of the memory pillar structures. A metal may be selectively grown upward from the physically exposed metal-nucleating surface while suppressing growth of the metal from physically exposed vertical surfaces around the memory pillar structures.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: August 25, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Raghuveer S. Makala, Adarsh Rajashekhar, Fei Zhou
  • Publication number: 20200243500
    Abstract: A support die includes complementary metal-oxide-semiconductor (CMOS) devices, front support-die bonding pads electrically connected to a first subset of the peripheral circuitry, and backside bonding structures electrically connected to a second subset of the peripheral circuitry. A first memory die including a first three-dimensional array of memory elements is bonded to the support die. First memory-die bonding pads of the first memory die are bonded to the front support-die bonding pads. A second memory die including a second three-dimensional array of memory elements is bonded to the support die. Second memory-die bonding pads of the second memory die are bonded to the backside bonding structures.
    Type: Application
    Filed: April 14, 2020
    Publication date: July 30, 2020
    Inventors: Fei Zhou, Raghuveer S. Makala, Adarsh Rajashekhar, Rahul Sharangpani
  • Publication number: 20200194446
    Abstract: Three-dimensional memory devices include structures that induce a vertical tensile stress in vertical semiconductor channels to enhance charge carrier mobility. Vertical tensile stress may be induced by a laterally compressive stress applied by stressor pillar structure. The stressor pillar structures can include a stressor material such as a dielectric metal oxide material, silicon nitride, thermal silicon oxide or a semiconductor material having a greater lattice constant than that of the channel. Vertical tensile stress may be induced by a compressive stress applied by electrically conductive layers that laterally surround the vertical semiconductor channel, or by a stress memorization technique that captures a compressive stress from sacrificial material layers. Vertical tensile stress can be generated by a source-level pinning layer that prevents vertical expansion of the vertical semiconductor channel.
    Type: Application
    Filed: December 17, 2018
    Publication date: June 18, 2020
    Inventors: Akio NISHIDA, Toshikazu IIZUKA, Rahul SHARANGPANI, Raghuveer S. MAKALA, Adarsh RAJASHEKHAR, Fei ZHOU, Srikanth RANGANATHAN
  • Publication number: 20200194445
    Abstract: Three-dimensional memory devices include structures that induce a vertical tensile stress in vertical semiconductor channels to enhance charge carrier mobility. Vertical tensile stress may be induced by a laterally compressive stress applied by stressor pillar structure. The stressor pillar structures can include a stressor material such as a dielectric metal oxide material, silicon nitride, thermal silicon oxide or a semiconductor material having a greater lattice constant than that of the channel. Vertical tensile stress may be induced by a compressive stress applied by electrically conductive layers that laterally surround the vertical semiconductor channel, or by a stress memorization technique that captures a compressive stress from sacrificial material layers. Vertical tensile stress can be generated by a source-level pinning layer that prevents vertical expansion of the vertical semiconductor channel.
    Type: Application
    Filed: December 17, 2018
    Publication date: June 18, 2020
    Inventors: Rahul SHARANGPANI, Raghuveer S. MAKALA, Adarsh RAJASHEKHAR, Fei ZHOU, Srikanth RANGANATHAN, Akio NISHIDA, Toshikazu IIZUKA
  • Publication number: 20200168619
    Abstract: In-process source-level material layers including a source-level sacrificial layer are formed over a substrate. An alternating stack of insulating layers and sacrificial material layers is formed over the in-process source-level material layers. A memory opening is formed through the alternating stack, and is filled with a memory film and a sacrificial opening fill structure. The source-level sacrificial layer is replaced with a source contact layer including a doped polycrystalline semiconductor material. The source contact layer can be formed by diffusing a metal in a metallic catalyst material through a semiconductor fill material layer that fills a source cavity formed by removal of the source-level sacrificial layer. The sacrificial opening fill structure is replaced with a vertical semiconductor channel, which can be formed with large grains due to large crystal sizes in the source contact layer. The sacrificial material layers are replaced with electrically conductive layers.
    Type: Application
    Filed: November 26, 2018
    Publication date: May 28, 2020
    Inventors: Fei ZHOU, Adarsh RAJASHEKHAR, Rahul SHARANGPANI, Raghuveer S. MAKALA
  • Patent number: 10665581
    Abstract: A support die includes complementary metal-oxide-semiconductor (CMOS) devices, front support-die bonding pads electrically connected to a first subset of the peripheral circuitry, and backside bonding structures electrically connected to a second subset of the peripheral circuitry. A first memory die including a first three-dimensional array of memory elements is bonded to the support die. First memory-die bonding pads of the first memory die are bonded to the front support-die bonding pads. A second memory die including a second three-dimensional array of memory elements is bonded to the support die. Second memory-die bonding pads of the second memory die are bonded to the backside bonding structures.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: May 26, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Fei Zhou, Raghuveer S. Makala, Adarsh Rajashekhar, Rahul Sharangpani
  • Publication number: 20200152655
    Abstract: A vertical repetition of a unit layer stack including an insulating layer, a sacrificial material layer, and a nucleation promoter layer is formed over a substrate. Memory stack structures are formed through the vertical repetition. Each of the memory stack structures comprises a memory film and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers and the nucleation promoter layers within the vertical repetition. Electrically conductive layers are formed in the backside recesses by selectively growing a metallic material from physically exposed surfaces of the nucleation promoter layers while suppressing growth of the metallic material from physically exposed surfaces of the insulating layers.
    Type: Application
    Filed: November 8, 2018
    Publication date: May 14, 2020
    Inventors: Rahul SHARANGPANI, Fei ZHOU, Raghuveer S. MAKALA, Adarsh RAJASHEKHAR
  • Patent number: 10651196
    Abstract: A vertical repetition of a unit layer stack including an insulating layer, a sacrificial material layer, and a nucleation promoter layer is formed over a substrate. Memory stack structures are formed through the vertical repetition. Each of the memory stack structures comprises a memory film and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers and the nucleation promoter layers within the vertical repetition. Electrically conductive layers are formed in the backside recesses by selectively growing a metallic material from physically exposed surfaces of the nucleation promoter layers while suppressing growth of the metallic material from physically exposed surfaces of the insulating layers.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: May 12, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Fei Zhou, Raghuveer S. Makala, Adarsh Rajashekhar
  • Patent number: 10615123
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate and memory stack structures extending through the alternating stack. Each of the electrically conductive layers includes a stack of a compositionally graded diffusion barrier and a metal fill material portion, and the compositionally graded diffusion barrier includes a substantially amorphous region contacting the interface between the compositionally graded diffusion barrier and a substantially crystalline region that is spaced from the interface by the amorphous region. The substantially crystalline region effectively blocks atomic diffusion, and the amorphous region induces formation of large grains during deposition of the metal fill material portions.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: April 7, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Tatsuya Hinoue, Tomoyuki Obu, Tomohiro Uno, Yusuke Mukae, Rahul Sharangpani, Raghuveer S. Makala, Fei Zhou, Adarsh Rajashekhar