Patents by Inventor Aditya Katragada
Aditya Katragada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240106644Abstract: A system and method of enhancing the mitigation of side channel attacks on platform interconnects using endpoint HW based detection, synchronization, and re-keying include generating a set of keys for link encryption based on a high entropy seed, storing the set of keys in a deterministic order in a register, detecting that a re-key programmable threshold is met during link encryption with a device, identifying a synchronization point associated with the device, where the synchronization point indicates the device is ready to switch a current key used for link encryption, and synchronizing a rekeying event with the device.Type: ApplicationFiled: September 27, 2022Publication date: March 28, 2024Applicant: Intel CorporationInventors: Aditya Katragada, Geoffrey Strongin, Prakash Iyer, Rajesh Banginwar, Poh Thiam Teoh, Gary Wallichs
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Patent number: 11928215Abstract: An apparatus to verify firmware in a computing system, comprising a non-volatile memory, including firmware memory to store agent firmware associated with each of a plurality of interconnect protocol (IP) agents and version memory to store security version numbers (SVNs) included in the agent firmware, a security controller comprising verifier logic to verify an integrity of the version memory by applying a hash algorithm to contents of the version memory to generate a SVN hash, and a trusted platform module (TPM) to store the SVN hash.Type: GrantFiled: June 29, 2022Date of Patent: March 12, 2024Assignee: Intel CorporationInventors: Prashant Dewan, Chao Zhang, Nivedita Aggarwal, Aditya Katragada, Mohamed Haniffa, Kenji Chen
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Patent number: 11886316Abstract: An apparatus to collect firmware measurement data at a computing system is disclosed. The apparatus includes a plurality of agents, each including a non-volatile memory storing firmware executed to perform a function associated with the agent, verification logic to generate measurement data by verifying the integrity of the firmware and a register to store the measurement data, and a processor to execute an instruction to collect firmware measurement data from each of the plurality of agents.Type: GrantFiled: April 29, 2022Date of Patent: January 30, 2024Assignee: Intel CorporationInventors: Prashant Dewan, Uttam Sengupta, Aditya Katragada
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Patent number: 11768941Abstract: An apparatus to implement an IP independent secure firmware load into an IP agent without a ROM to establish hardware root of trust is disclosed. The apparatus includes a plurality of agents, at least one agent including an isolated memory region accessible only to a trusted entity of the at least one agent and a main memory, and a processor to allocate a section of the isolated memory region of the at least one agent, verify a first stage firmware module, the first stage firmware module comprising instructions to enable the at least one agent to load and verify a second stage firmware module, place the first stage firmware module into memory of the at least one agent without a ROM to establish the hardware root of trust.Type: GrantFiled: March 27, 2020Date of Patent: September 26, 2023Assignee: INTEL CORPORATIONInventors: Vinupama Godavarthi, Andrzej Mialkowski, Kar Leong Wong, Aditya Katragada, Maciej Kusio, Prashant Dewan, Karunakara Kotary
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Patent number: 11734457Abstract: A processor that was manufactured by a manufacturer comprises privileged debug operational circuitry, a debug restriction fuse, a credential store, a credential of the manufacturer in the credential store, and debug control circuitry. The debug restriction fuse is a one-time programmable fuse. The debug control circuitry is to automatically restrict access to the privileged debug operational circuitry, based on the debug restriction fuse. The processor may also include public debug operational circuitry, a prevent-unauthorized-debug (PUD) fuse, and an undo-PUD fuse. When the PUD fuse is set and the undo-PUD fuse is clear, the debug control circuitry may respond to an attempt by a debugger to use the public debug operational circuitry by determining whether the debugger is authorized, disallowing access if the debugger is not authorized, and allowing access if the debugger is authorized. Other embodiments are described and claimed.Type: GrantFiled: December 23, 2019Date of Patent: August 22, 2023Assignee: Intel CorporationInventors: Neel Piyush Shah, Enrico David Carrieri, Aditya Katragada, Jonathan Mark Lutz, Michael Carl Neve de Mevergnies, Bhavana Prabhakar
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Publication number: 20230169173Abstract: An integrated circuit provides a firmware dashboard to communicatively couple to a basic input/output system (BIOS), and provide to the BIOS a firmware load interface, and an intellectual property (IP) block interface to communicatively couple to an IP block, wherein the IP block provides a push model to load a firmware or a pull model to load the firmware, and wherein the firmware dashboard provides a common load flow to the BIOS for both the push model and pull model.Type: ApplicationFiled: December 26, 2022Publication date: June 1, 2023Applicant: Intel CorporationInventors: Aditya Katragada, Prashant Dewan, Karunakara Kotary, Vinupama Godavarthi, Kumar Dwarakanath, Alex Izbinsky, Purushottam Goel
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Patent number: 11550917Abstract: There is disclosed in one example, a system-on-a-chip (SoC), including: a processor core; a fabric; an intellectual property (IP) block communicatively coupled to the processor core via the fabric, the IP block having a microcontroller configured to provide a microcontroller architecture; a firmware load interface configured to provide a standardized hardware interface to the microcontroller architecture, wherein the standardized hardware interface provides an architecture-agnostic mechanism to securely load a firmware to the intellectual property block; and logic to provide a loader to load a firmware to the IP block via the firmware load interface.Type: GrantFiled: June 28, 2019Date of Patent: January 10, 2023Assignee: Intel CorporationInventors: Aditya Katragada, Prashant Dewan, Karunakara Kotary, Vinupama Godavarthi, Kumar Dwarakanath, Alex Izbinsky, Purushottam Goel
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Publication number: 20220327214Abstract: An apparatus to verify firmware in a computing system, comprising a non-volatile memory, including firmware memory to store agent firmware associated with each of a plurality of interconnect protocol (IP) agents and version memory to store security version numbers (SVNs) included in the agent firmware, a security controller comprising verifier logic to verify an integrity of the version memory by applying a hash algorithm to contents of the version memory to generate a SVN hash, and a trusted platform module (TPM) to store the SVN hash.Type: ApplicationFiled: June 29, 2022Publication date: October 13, 2022Applicant: Intel CorporationInventors: Prashant Dewan, Chao Zhang, Nivedita Aggarwal, Aditya Katragada, Mohamed Haniffa, Kenji Chen
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Publication number: 20220283959Abstract: Techniques are described for providing consistent memory operations and security across electronic circuitry components having disparate memory and/or security architectures when integrating such disparately architected components within a single system, such as a system on chip. A programmable logical hierarchy of isolated memory region (IMR) enforcement circuits is provided to protect such IMRs, allowing or preventing memory access requests from one of multiple distinct circuitry components based on configuration registers for the IMR enforcement circuits. Integration of multiple trust domain architectures associated with the multiple distinct circuitry components is facilitated via trust domain conversion bridge circuitry that includes translation logic for generating information in accordance with a first trust domain architecture based on information provided in accordance with a distinct second trust domain architecture.Type: ApplicationFiled: March 21, 2022Publication date: September 8, 2022Applicant: Intel CorporationInventors: Aditya Katragada, Peter Munguia, Gregg Lahti
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Patent number: 11416370Abstract: An apparatus to collect firmware measurement data at a computing system is disclosed. The apparatus includes a plurality of agents, each including a non-volatile memory storing firmware executed to perform a function associated with the agent, verification logic to generate measurement data by verifying the integrity of the firmware and a register to store the measurement data, and a processor to execute an instruction to collect firmware measurement data from each of the plurality of agents.Type: GrantFiled: March 27, 2020Date of Patent: August 16, 2022Assignee: Intel CorporationInventors: Prashant Dewan, Uttam Sengupta, Aditya Katragada
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Publication number: 20220253366Abstract: An apparatus to collect firmware measurement data at a computing system is disclosed. The apparatus includes a plurality of agents, each including a non-volatile memory storing firmware executed to perform a function associated with the agent, verification logic to generate measurement data by verifying the integrity of the firmware and a register to store the measurement data, and a processor to execute an instruction to collect firmware measurement data from each of the plurality of agents.Type: ApplicationFiled: April 29, 2022Publication date: August 11, 2022Applicant: Intel CorporationInventors: Prashant Dewan, Uttam Sengupta, Aditya Katragada
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Patent number: 11409877Abstract: An apparatus to verify firmware in a computing system, comprising a non-volatile memory, including firmware memory to store agent firmware associated with each of a plurality of interconnect protocol (IP) agents and version memory to store security version numbers (SVNs) included in the agent firmware, a security controller comprising verifier logic to verify an integrity of the version memory by applying a hash algorithm to contents of the version memory to generate a SVN hash, and a trusted platform module (TPM) to store the SVN hash.Type: GrantFiled: March 27, 2020Date of Patent: August 9, 2022Assignee: Intel CorporationInventors: Prashant Dewan, Chao Zhang, Nivedita Aggarwal, Aditya Katragada, Mohamed Haniffa, Kenji Chen
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Publication number: 20220150046Abstract: A security processor includes a scheduler to read input data blocks from an input buffer, send the input data blocks to one or more cryptographic circuits in a first random order; and send data blocks having random values in a second random order to one or more of the cryptographic circuits that did not receive the input data blocks.Type: ApplicationFiled: September 16, 2021Publication date: May 12, 2022Applicant: Intel CorporationInventors: Dumitru-Daniel Dinu, Emre Karabulut, Aditya Katragada, Geoffrey Strongin, Avinash L. Varna
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Patent number: 11281595Abstract: Techniques are described for providing consistent memory operations and security across electronic circuitry components having disparate memory and/or security architectures when integrating such disparately architected components within a single system, such as a system on chip. A programmable logical hierarchy of isolated memory region (IMR) enforcement circuits is provided to protect such IMRs, allowing or preventing memory access requests from one of multiple distinct circuitry components based on configuration registers for the IMR enforcement circuits. Integration of multiple trust domain architectures associated with the multiple distinct circuitry components is facilitated via trust domain conversion bridge circuitry that includes translation logic for generating information in accordance with a first trust domain architecture based on information provided in accordance with a distinct second trust domain architecture.Type: GrantFiled: May 28, 2018Date of Patent: March 22, 2022Assignee: Intel CorporationInventors: Aditya Katragada, Peter Munguia, Gregg Lahti
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Publication number: 20210303692Abstract: An apparatus to implement an IP independent secure firmware load into an IP agent without a ROM to establish hardware root of trust is disclosed.Type: ApplicationFiled: March 27, 2020Publication date: September 30, 2021Applicant: Intel CorporationInventors: Vinupama Godavarthi, Andrzej Mialkowski, Kar Leong Wong, Aditya Katragada, Maciej Kusio, Prashant Dewan, Karunakara Kotary
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Publication number: 20210303691Abstract: An apparatus to implement an IP independent firmware load is disclosed. The apparatus includes a plurality of agents, a plurality of agents, at least one agent including a memory to store firmware to be executed by the agent to perform a function associated with the agent and a register to store enumeration data for the firmware load mechanism of the IP, and a processor to initiate an enumeration process to read the enumeration data from the register of the at least one agent, make a decision based on that data to retrieve a firmware module from a storage device, verify the firmware module, and load the firmware module into the memory of the at least one agent.Type: ApplicationFiled: March 27, 2020Publication date: September 30, 2021Applicant: Intel CorporationInventors: Prashant Dewan, Karunakara Kotary, Nivedita Aggarwal, Vinupama Godavarthi, Aditya Katragada, Mohamed Haniffa, Tung Lun Loo
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Publication number: 20210192085Abstract: A processor that was manufactured by a manufacturer comprises privileged debug operational circuitry, a debug restriction fuse, a credential store, a credential of the manufacturer in the credential store, and debug control circuitry. The debug restriction fuse is a one-time programmable fuse. The debug control circuitry is to automatically restrict access to the privileged debug operational circuitry, based on the debug restriction fuse. The processor may also include public debug operational circuitry, a prevent-unauthorized-debug (PUD) fuse, and an undo-PUD fuse. When the PUD fuse is set and the undo-PUD fuse is clear, the debug control circuitry may respond to an attempt by a debugger to use the public debug operational circuitry by determining whether the debugger is authorized, disallowing access if the debugger is not authorized, and allowing access if the debugger is authorized. Other embodiments are described and claimed.Type: ApplicationFiled: December 23, 2019Publication date: June 24, 2021Inventors: Neel Piyush Shah, Enrico David Carrieri, Aditya Katragada, Jonathan Mark Lutz, Michael Carl Neve de Mevergnies, Bhavana Prabhakar
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Publication number: 20200226261Abstract: An apparatus to verify firmware in a computing system, comprising a non-volatile memory, including firmware memory to store agent firmware associated with each of a plurality of interconnect protocol (IP) agents and version memory to store security version numbers (SVNs) included in the agent firmware, a security controller comprising verifier logic to verify an integrity of the version memory by applying a hash algorithm to contents of the version memory to generate a SVN hash, and a trusted platform module (TPM) to store the SVN hash.Type: ApplicationFiled: March 27, 2020Publication date: July 16, 2020Applicant: Intel CorporationInventors: Prashant Dewan, Chao Zhang, Nivedita Aggarwal, Aditya Katragada, Mohamed Haniffa, Kenji Chen
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Publication number: 20200226047Abstract: An apparatus to collect firmware measurement data at a computing system is disclosed. The apparatus includes a plurality of agents, each including a non-volatile memory storing firmware executed to perform a function associated with the agent, verification logic to generate measurement data by verifying the integrity of the firmware and a register to store the measurement data, and a processor to execute an instruction to collect firmware measurement data from each of the plurality of agents.Type: ApplicationFiled: March 27, 2020Publication date: July 16, 2020Applicant: Intel CorporationInventors: Prashant Dewan, Uttam Sengupta, Aditya Katragada
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Publication number: 20190318097Abstract: There is disclosed in one example, a system-on-a-chip (SoC), including: a processor core; a fabric; an intellectual property (IP) block communicatively coupled to the processor core via the fabric, the IP block having a microcontroller configured to provide a microcontroller architecture; a firmware load interface configured to provide a standardized hardware interface to the microcontroller architecture, wherein the standardized hardware interface provides an architecture-agnostic mechanism to securely load a firmware to the intellectual property block; and logic to provide a loader to load a firmware to the IP block via the firmware load interface.Type: ApplicationFiled: June 28, 2019Publication date: October 17, 2019Inventors: Aditya Katragada, Prashant Dewan, Karunakara Kotary, Vinupama Godavarthi, Kumar Dwarakanath, Alex Izbinsky, Purushottam Goel