Abstract: Techniques are described for providing consistent memory operations and security across electronic circuitry components having disparate memory and/or security architectures when integrating such disparately architected components within a single system, such as a system on chip. A programmable logical hierarchy of isolated memory region (IMR) enforcement circuits is provided to protect such IMRs, allowing or preventing memory access requests from one of multiple distinct circuitry components based on configuration registers for the IMR enforcement circuits. Integration of multiple trust domain architectures associated with the multiple distinct circuitry components is facilitated via trust domain conversion bridge circuitry that includes translation logic for generating information in accordance with a first trust domain architecture based on information provided in accordance with a distinct second trust domain architecture.

Abstract: In one example, a system for managing access to hardware components includes a processor to manage a transition of a component from a known trusted first state and a context of a first application to a known trusted second state and a context of a second application based on trusted meta-data. The processor can also prevent contamination across the known trusted state of each application based on the trusted meta-data associated with each application. Additionally, the processor can detect a change of a trust boundary from the first application to the second application, save the first state of the first application accessing the component, remove said first state from the component, initialize and load the second state of the second application accessing the component, and execute the second application via the component based on the second state.