Patents by Inventor Aditya Kulkarni

Aditya Kulkarni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170124123
    Abstract: Presented herein are methods, non-transitory computer readable media, and devices for efficiently administering locks for shared resources, such as data blocks, stored on a storage system. Methods for stamping a plurality of computer data objects are disclosed which include: accessing at least one of the plurality of computer data objects by a first data thread; assigning, by the first data thread, a stamp to the at least one of the plurality of computer data objects, to signify the at least one of the plurality of computer data objects is associated with the first data thread; preventing subsequent access by a second data thread to the stamped at least one of the plurality of computer data objects; and determining the stamp is no longer active, upon an event, effectively releasing the at least one of the plurality of computer data objects.
    Type: Application
    Filed: October 30, 2015
    Publication date: May 4, 2017
    Inventors: Matthew CURTIS-MAURY, Aditya KULKARNI, Vinay DEVADAS
  • Patent number: 9526802
    Abstract: The invention relates to nucleic acid complexes, methods of preparation thereof, and uses thereof for delivering a nucleic acid into a cell.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: December 27, 2016
    Assignee: Purdue Research Foundation
    Inventors: David H. Thompson, Aditya Kulkarni, Wei Deng
  • Patent number: 9390009
    Abstract: A configuration mapping system and method increase the effectiveness of mapping of information from an established product line to a new product offering. In at least one embodiment, the configuration mapping system herein uses configuration mapping rules to map individual product features and entire configurations from established products to a new product offering. The configuration mapping system also provides a way to appropriately map, for example, demand and sales information for the purpose of demand estimation and sales prediction. Conventionally, mapping can be ineffective because the configuration mapping rules usually focus on one part of the product at a time, and, if applied in isolation, the impact on other parts is missed. The systems and method herein provide a way to integrate configuration mapping rules across feature parts, time periods, and product lines into a unified, holistic view, allowing for new insights.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: July 12, 2016
    Assignee: Trilogy Intellectual Property Holdings, Inc.
    Inventors: Aditya Kulkarni, Sourabh Kukreja
  • Publication number: 20160083485
    Abstract: Various embodiments of the present invention are directed to polyrotaxanes comprising a poloxamer core and at least one cyclodextrin and methods for treating Niemann-Pick type C (NPC) and imaging (e.g., MRI) using the polyrotaxanes various embodiments of the present invention.
    Type: Application
    Filed: May 7, 2014
    Publication date: March 24, 2016
    Inventors: David H. Thompson, Aditya Kulkarni, Christopher Collins, Yawo Mondjinou
  • Publication number: 20150202323
    Abstract: The invention relates to nucleic acid complexes, methods of preparation thereof, and uses thereof for delivering a nucleic acid into a cell.
    Type: Application
    Filed: November 17, 2014
    Publication date: July 23, 2015
    Inventors: David H. Thompson, Aditya Kulkarni, Wei Deng
  • Patent number: 8916697
    Abstract: The invention relates to nucleic acid complexes, methods of preparation thereof, and uses thereof for delivering a nucleic acid into a cell.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: December 23, 2014
    Assignee: Purdue Research Foundation
    Inventors: David H. Thompson, Aditya Kulkarni, Wei Deng
  • Publication number: 20140188952
    Abstract: A server that caches data in a storage system includes a data access manager that accesses data with a physical location identifier instead of a logical block reference identifier used by a filesystem that manages the cached data. The data access manager provisions a buffer from a pool of buffers maintained by the filesystem, and associates the provisioned buffer with a cache location separate from a buffer cache maintained by the filesystem. The data access manager issues a read for the data with the physical location identifier to obtain the data, and stores the data in the cache location separate from the buffer cache in the provisioned buffer. The data access manager performs a validity check on the obtained data and discards the obtained data when the validity check fails. The data access manager provides access to the buffer to a requesting program.
    Type: Application
    Filed: March 15, 2013
    Publication date: July 3, 2014
    Inventors: PRAVEEN KILLAMSETTI, Subramaniam Periagaram, Aditya Kulkarni
  • Publication number: 20130261168
    Abstract: The invention relates to nucleic acid complexes, methods of preparation thereof, and uses thereof for delivering a nucleic acid into a cell.
    Type: Application
    Filed: March 14, 2013
    Publication date: October 3, 2013
    Inventors: David H. THOMPSON, Aditya KULKARNI, Wei DENG
  • Publication number: 20130132701
    Abstract: A configuration mapping system and method increase the effectiveness of mapping of information from an established product line to a new product offering. In at least one embodiment, the configuration mapping system herein uses configuration mapping rules to map individual product features and entire configurations from established products to a new product offering. The configuration mapping system also provides a way to appropriately map, for example, demand and sales information for the purpose of demand estimation and sales prediction. Conventionally, mapping can be ineffective because the configuration mapping rules usually focus on one part of the product at a time, and, if applied in isolation, the impact on other parts is missed. The systems and method herein provide a way to integrate configuration mapping rules across feature parts, time periods, and product lines into a unified, holistic view, allowing for new insights.
    Type: Application
    Filed: January 16, 2013
    Publication date: May 23, 2013
    Applicant: TRILOGY INTELECTUAL PROPERTY HOLDINGS, INC.
    Inventors: Aditya Kulkarni, Sourabh Kukreja
  • Patent number: 7634776
    Abstract: A method for designing a multi-threaded processing operation that includes, e.g., multimedia encoding/decoding, uses an architecture having multiple processors and optional hardware accelerators. The method includes the steps of: identifying a desired chronological sequence of processing stages for processing input data including identifying interdependencies of said processing stages; allotting each said processing sage to a processor; staggering the processing to accommodate the interdependencies; selecting a processing operation based on said allotting to arrive at a subset of possible pipelines that offer low average processing time; and, choosing one design pipeline from said subset to result in overall timing reduction to complete said processing operation. The invention provides a multi-threaded processing pipeline that is applicable in a System-on-Chip (SoC) using a DSP and shared resources such as DMA controller and on-chip memory, for increasing the throughput.
    Type: Grant
    Filed: May 12, 2005
    Date of Patent: December 15, 2009
    Assignee: Ittiam Systems (P) Ltd.
    Inventors: Sankaranarayanan Parameswaran, Sriram Sethuraman, Manish Singhal, Dileep Kumar Tamia, Dinesh Kumar, Aditya Kulkarni, Murali Babu Muthukrishnan
  • Publication number: 20050262510
    Abstract: A method for designing a multi-threaded processing operation that includes, e.g., multimedia encoding/decoding, uses an architecture having multiple processors and optional hardware accelerators. The method includes the steps of: identifying a desired chronological sequence of processing stages for processing input data including identifying interdependencies of said processing stages; allotting each said processing sage to a processor; staggering the processing to accommodate the interdependencies; selecting a processing operation based on said allotting to arrive at a subset of possible pipelines that offer low average processing time; and, choosing one design pipeline from said subset to result in overall timing reduction to complete said processing operation. The invention provides a multi-threaded processing pipeline that is applicable in a System-on-Chip (SoC) using a DSP and shared resources such as DMA controller and on-chip memory, for increasing the throughput.
    Type: Application
    Filed: May 12, 2005
    Publication date: November 24, 2005
    Inventors: Sankaranarayanan Parameswaran, Sriram Sethuraman, Manish Singhal, Dileep Tamia, Dinesh Kumar, Aditya Kulkarni, Murali Muthukrishnan