Patents by Inventor Aditya Navale

Aditya Navale has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160147668
    Abstract: A method and apparatus for creating, updating, and using guest physical address (GPA) to host physical address (HPA) shadow translation tables for translating GPAs of graphics data direct memory access (DMA) requests of a computing environment implementing a virtual machine monitor to support virtual machines. The requests may be sent through a render or display path of the computing environment from one or more virtual machines, transparently with respect to the virtual machine monitor. The creating, updating, and using may be performed by a memory controller detecting entries sent to existing global and page directory tables, forking off shadow table entries from the detected entries, and translating GPAs to HPAs for the shadow table entries.
    Type: Application
    Filed: December 9, 2015
    Publication date: May 26, 2016
    Inventors: Balaji Vembu, Aditya Navale, Wishwesh Gandhi
  • Patent number: 9323684
    Abstract: Technologies are presented that allow a portion of a cache to be used as a front memory when there is dynamic need based on system demand. A computing system may include at least one processor, a memory controlled by a controller and communicatively coupled with the at least one processor, a cache communicatively coupled with the at least one processor and the memory, and mapping logic communicatively coupled with the at least one processor, the memory, and the cache. The mapping logic may map a portion of the cache to a portion of the memory, wherein the portion of the cache is to be used by the at least one processor as a local memory, and wherein the mapping is dynamic based on system demand and managed by the controller in a physical address domain.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: April 26, 2016
    Assignee: Intel Corporation
    Inventors: Altug Koker, Aditya Navale
  • Patent number: 9304813
    Abstract: A computing device for performing scheduling operations for graphics hardware is described herein. The computing device includes a central processing unit (CPU) that is configured to execute an application. The computing device also includes a graphics scheduler configured to operate independently of the CPU. The graphics scheduler is configured to receive work queues relating to workloads from the application that are to execute on the CPU and perform scheduling operations for any of a number of graphics engines based on the work queues.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: April 5, 2016
    Assignee: Intel Corporation
    Inventors: Balaji Vembu, Aditya Navale, Murali Ramadoss, David I. Standring, Kritika Bala
  • Publication number: 20160062451
    Abstract: A method includes detecting a trigger condition, and in response to detecting the trigger condition, reducing a voltage applied to a graphics controller component of a memory controller. The reduction in voltage may cause the voltage to be reduced below a voltage level required to maintain context information in the graphics controller component.
    Type: Application
    Filed: November 10, 2015
    Publication date: March 3, 2016
    Inventors: Eric C. Samson, Aditya Navale
  • Patent number: 9268691
    Abstract: A mechanism implemented by a controller enables efficient access to an interleaved memory system that includes M modules, M being (2n+1) or (2n?1), n being a positive integer number. Upon receiving an address N, the controller performs shift and add/subtract operations to obtain a quotient of N divided by M based on a binomial series expansion of N over M. The controller computes a remainder of N divided by M based on the quotient. The controller then accesses one of the modules in the memory based on the remainder.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: February 23, 2016
    Assignee: Intel Corporation
    Inventors: Saurabh Sharma, Altug Koker, Aditya Navale
  • Patent number: 9223603
    Abstract: A method and apparatus for creating, updating, and using guest physical address (GPA) to host physical address (HPA) shadow translation tables for translating GPAs of graphics data direct memory access (DMA) requests of a computing environment implementing a virtual machine monitor to support virtual machines. The requests may be sent through a render or display path of the computing environment from one or more virtual machines, transparently with respect to the virtual machine monitor. The creating, updating, and using may be performed by a memory controller detecting entries sent to existing global and page directory tables, forking off shadow table entries from the detected entries, and translating GPAs to HPAs for the shadow table entries.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: December 29, 2015
    Assignee: Intel Corporation
    Inventors: Balaji Vembu, Aditya Navale, Wishwesh Gandhi
  • Patent number: 9213395
    Abstract: A method includes detecting a trigger condition, and in response to detecting the trigger condition, reducing a voltage applied to a graphics controller component of a memory controller. The reduction in voltage may cause the voltage to be reduced below a voltage level required to maintain context information in the graphics controller component.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: December 15, 2015
    Assignee: INTEL CORPORATION
    Inventors: Eric C. Samson, Aditya Navale
  • Publication number: 20150277981
    Abstract: Methods and apparatuses may prioritize the processing of high priority and low priority contexts submitted to a processing unit through separate high priority and low priority context submission ports. According to one embodiment, submission of a context to the low priority port causes contexts in progress to be preempted, whereas submission of a context to the high priority port causes contexts in progress to be paused.
    Type: Application
    Filed: March 27, 2014
    Publication date: October 1, 2015
    Inventors: Hema C. Nalluri, Aditya Navale, Peter L. Doyle, Murali Ramadoss, Balaji Vembu, Jeffery S. Boles
  • Publication number: 20150278984
    Abstract: Methods and systems may provide for executing, by a physically distributed set of compute slices, a plurality of work items. Additionally, the coherency of one or more memory lines associated with the plurality of work items may be maintained, by a cache fabric, across a graphics processor, a system memory and one or more host processors. In one example, a plurality of crossbar nodes track the one or more memory lines, wherein the coherency of the one or more memory lines is maintained across a plurality of level one (L1) caches and a physically distributed cache structure. Each L1 cache may be dedicated to an execution block of a compute slice and each crossbar node may be dedicated to a compute slice.
    Type: Application
    Filed: March 27, 2014
    Publication date: October 1, 2015
    Inventors: Altug Koker, Aditya Navale
  • Publication number: 20150269083
    Abstract: Technologies are presented that allow a portion of a cache to be used as a front memory when there is dynamic need based on system demand. A computing system may include at least one processor, a memory controlled by a controller and communicatively coupled with the at least one processor, a cache communicatively coupled with the at least one processor and the memory, and mapping logic communicatively coupled with the at least one processor, the memory, and the cache. The mapping logic may map a portion of the cache to a portion of the memory, wherein the portion of the cache is to be used by the at least one processor as a local memory, and wherein the mapping is dynamic based on system demand and managed by the controller in a physical address domain.
    Type: Application
    Filed: March 21, 2014
    Publication date: September 24, 2015
    Inventors: Altug Koker, Aditya Navale
  • Patent number: 9075741
    Abstract: Embodiments of an invention for dynamic error correction using parity and redundant rows are disclosed. In one embodiment, an apparatus includes a storage structure, parity logic, an error storage space, and an error event generator. The storage structure is to store a plurality of data values. The parity logic is to detect a parity error in a data value stored in the storage structure. The error storage space is to store an indication of a detection of the parity error. The error event generator is to generate an event in response to the indication of the parity error being stored in the error storage space.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: July 7, 2015
    Assignee: Intel Corporation
    Inventors: Altug Koker, Shailesh Shah, Aditya Navale, Murali Ramadoss, Satish K. Damaraju
  • Patent number: 9064437
    Abstract: Memory-based semaphore are described that are useful for synchronizing operations between different processing engines. In one example, operations include executing a context at a producer engine, the executing including updating a memory register, and sending a signal from the producer engine to a consumer engine that the memory register has been updated, the signal including a Context ID to identify a context to be executed by the consumer engine to update the register.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: June 23, 2015
    Assignee: Intel Corporation
    Inventors: Hema Chand Nalluri, Aditya Navale
  • Publication number: 20150123980
    Abstract: A method and apparatus for supporting programmable software context state execution during hardware context restore flow is described. In one example, a context ID is assigned to graphics applications including a unique context memory buffer, a unique indirect context pointer and a corresponding size to each context ID, an indirect context offset, and an indirect context buffer address range. When execution of the first context workload is indirected, the state of the first context workload is saved to the assigned context memory buffer. The indirect context pointer, the indirect context offset and a size of the indirect context buffer address range are saved to registers that are independent of the saved context state. The context is restored by accessing the saved indirect context pointer, the indirect context offset and the buffer size.
    Type: Application
    Filed: November 5, 2013
    Publication date: May 7, 2015
    Inventors: Hema Chand Nalluri, Jeffery S. Boles, Murali Ramadoss, Aditya Navale, Lalit K. Saptarshi
  • Publication number: 20150103084
    Abstract: Methods and systems may provide for storing a set of post-synchronization operations to a graphics memory and sending a flush marker to a graphics pipeline. Additionally, the set of post-synchronization operations may be processed in response to the flush marker exiting the graphics pipeline. In one example, the set of post-synchronization operations includes one or more atomic operations. Moreover, the set of post-synchronization operations may be obtained from an inline portion of an atomics command.
    Type: Application
    Filed: October 10, 2013
    Publication date: April 16, 2015
    Inventors: Hema C. Nalluri, Aditya Navale, Altug Koker
  • Publication number: 20150012768
    Abstract: A method includes detecting a trigger condition, and in response to detecting the trigger condition, reducing a voltage applied to a graphics controller component of a memory controller. The reduction in voltage may cause the voltage to be reduced below a voltage level required to maintain context information in the graphics controller component.
    Type: Application
    Filed: September 26, 2014
    Publication date: January 8, 2015
    Inventors: Eric C. Samson, Aditya Navale
  • Publication number: 20150002522
    Abstract: Mid-command buffer preemption is described for graphics workloads in a graphics processing environment. In one example, instructions of a first context are executed at a graphics processor, the first context has a sequence of instructions in an addressable buffer and at least one of the instructions is a preemption instruction. Upon executing the preemption instruction, execution of the first context is stopped before the sequence of instructions is completed. An address is stored for an instruction with which the first context will be resumed. The second context is executed, and upon completion of the execution of the second context, the execution of the first context is resumed at the stored address.
    Type: Application
    Filed: June 29, 2013
    Publication date: January 1, 2015
    Inventors: Hema Chand Nalluri, Aditya Navale, Murali Ramadoss, Jeffery S. Boles
  • Publication number: 20140375661
    Abstract: Systems and methods may provide for identifying a tile associated with an image and ordering an entirety of the tile into a linear stream of pages associated with a frame buffer. Additionally, the linear stream of pages may be allocated to a cache. In one example, the linear stream of pages is allocated to the cache in accordance with a fixed set selection policy of the cache.
    Type: Application
    Filed: June 24, 2013
    Publication date: December 25, 2014
    Inventors: Altug Koker, Aditya Navale
  • Publication number: 20140306949
    Abstract: Systems, apparatus and methods are described including distributing batches of geometric objects to a multi-core system, at each processor core, performing vertex processing and geometry setup processing on the corresponding batch of geometric objects, storing the vertex processing results shared memory accessible to all of the cores, and storing the geometry setup processing results in local storage. Each particular core may then perform rasterization using geometry setup results obtained from local storage within the particular core and from local storage of at least one of the other processor cores.
    Type: Application
    Filed: November 18, 2011
    Publication date: October 16, 2014
    Inventors: Peter L. Doyle, Jeffery S. Boles, Arthur D. Hunter Jr., Altug Koker, Aditya Navale
  • Patent number: 8850254
    Abstract: A method includes detecting a trigger condition, and in response to detecting the trigger condition, reducing a voltage applied to a graphics controller component of a memory controller. The reduction in voltage may cause the voltage to be reduced below a voltage level required to maintain context information in the graphics controller component.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: September 30, 2014
    Assignee: Intel Corporation
    Inventors: Eric C. Samson, Aditya Navale
  • Publication number: 20140267323
    Abstract: An electronic device is described herein. The electronic device may include a page walker module to receive a page request of a graphics processing unit (GPU). The page walker module may detect a page fault associated with the page request. The electronic device may include a controller, at least partially comprising hardware logic. The controller is to monitor execution of the page request having the page fault. The controller determines whether to suspend execution of a work item at the GPU associated with the page request having the page fault, or to continue execution of the work item based on factors associated with the page request.
    Type: Application
    Filed: March 27, 2013
    Publication date: September 18, 2014
    Inventors: Altug Koker, Balaji Vembu, Murali Ramadoss, Aditya Navale