Patents by Inventor Aditya Navale

Aditya Navale has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140160138
    Abstract: Memory-based semaphore are described that are useful for synchronizing operations between different processing engines. In one example, operations include executing a context at a producer engine, the executing including updating a memory register, and sending a signal from the producer engine to a consumer engine that the memory register has been updated, the signal including a Context ID to identify a context to be executed by the consumer engine to update the register.
    Type: Application
    Filed: December 7, 2012
    Publication date: June 12, 2014
    Inventors: Hema Chand Nalluri, Aditya Navale
  • Publication number: 20140104287
    Abstract: Techniques are disclosed for processing rendering engine workload of a graphics system in a secure fashion, wherein at least some security processing of the workload is offloaded from software-based security parsing to hardware-based security parsing. In some embodiments, commands from a given application are received by a user mode driver (UMD), which is configured to generate a command buffer delineated into privileged and/or non-privileged command sections. The delineated command buffer can then be passed by the UMD to a kernel-mode driver (KMD), which is configured to parse and validate only privileged buffer sections, but to issue all other batch buffers with a privilege indicator set to non-privileged.
    Type: Application
    Filed: October 11, 2012
    Publication date: April 17, 2014
    Inventors: Hema C. Nalluri, Aditya Navale, Murali Ramadoss
  • Publication number: 20140068626
    Abstract: Transitions to ring 0, each time an application wants to use an adjunct processor, are avoided, saving central processor operating cycles and improving efficiency. Instead, initially each application is registered and setup to use adjunct processor resources in ring 3.
    Type: Application
    Filed: December 30, 2011
    Publication date: March 6, 2014
    Inventors: Altug Koker, Aditya Navale, Balaji Vembu, Murali Ramadoss
  • Publication number: 20140032954
    Abstract: A method includes detecting a trigger condition, and in response to detecting the trigger condition, reducing a voltage applied to a graphics controller component of a memory controller. The reduction in voltage may cause the voltage to be reduced below a voltage level required to maintain context information in the graphics controller component.
    Type: Application
    Filed: July 11, 2013
    Publication date: January 30, 2014
    Inventors: Eric C. Samson, Aditya Navale
  • Publication number: 20140025908
    Abstract: A mechanism implemented by a controller enables efficient access to an interleaved memory system that includes M modules, M being (2n+1) or (2n?1), n being a positive integer number. Upon receiving an address N, the controller performs shift and add/subtract operations to obtain a quotient of N divided by M based on a binomial series expansion of N over M. The controller computes a remainder of N divided by M based on the quotient. The controller then accesses one of the modules in the memory based on the remainder.
    Type: Application
    Filed: June 11, 2012
    Publication date: January 23, 2014
    Inventors: Saurabh Sharma, Altug Koker, Aditya Navale
  • Publication number: 20140026137
    Abstract: A computing device for performing scheduling operations for graphics hardware is described herein. The computing device includes a central processing unit (CPU) that is configured to execute an application. The computing device also includes a graphics scheduler configured to operate independently of the CPU. The graphics scheduler is configured to receive work queues relating to workloads from the application that are to execute on the CPU and perform scheduling operations for any of a number of graphics engines based on the work queues.
    Type: Application
    Filed: July 18, 2012
    Publication date: January 23, 2014
    Inventors: Balaji Vembu, Aditya Navale, Murali Ramadoss, David I. Standring, Kritika Bala
  • Publication number: 20130298124
    Abstract: A method and apparatus for creating, updating, and using guest physical address (GPA) to host physical address (HPA) shadow translation tables for translating GPAs of graphics data direct memory access (DMA) requests of a computing environment implementing a virtual machine monitor to support virtual machines. The requests may be sent through a render or display path of the computing environment from one or more virtual machines, transparently with respect to the virtual machine monitor. The creating, updating, and using may be performed by a memory controller detecting entries sent to existing global and page directory tables, forking off shadow table entries from the detected entries, and translating GPAs to HPAs for the shadow table entries.
    Type: Application
    Filed: July 1, 2013
    Publication date: November 7, 2013
    Inventors: Balaji Vembu, Aditya Navale, Wishwesh Gandhi
  • Patent number: 8510585
    Abstract: A method includes detecting a trigger condition, and in response to detecting the trigger condition, reducing a voltage applied to a graphics controller component of a memory controller. The reduction in voltage may cause the voltage to be reduced below a voltage level required to maintain context information in the graphics controller component.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: August 13, 2013
    Assignee: Intel Corporation
    Inventors: Eric C. Samson, Aditya Navale
  • Patent number: 8477145
    Abstract: A method and apparatus for creating, updating, and using guest physical address (GPA) to host physical address (HPA) shadow translation tables for translating GPAs of graphics data direct memory access (DMA) requests of a computing environment implementing a virtual machine monitor to support virtual machines. The requests may be sent through a render or display path of the computing environment from one or more virtual machines, transparently with respect to the virtual machine monitor. The creating, updating, and using may be performed by a memory controller detecting entries sent to existing global and page directory tables, forking off shadow table entries from the detected entries, and translating GPAs to HPAs for the shadow table entries.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: July 2, 2013
    Assignee: Intel Corporation
    Inventors: Balaji Vembu, Aditya Navale, Wishwesh Gandhi
  • Publication number: 20130159820
    Abstract: Embodiments of an invention for dynamic error correction using parity and redundant rows are disclosed. In one embodiment, an apparatus includes a storage structure, parity logic, an error storage space, and an error event generator. The storage structure is to store a plurality of data values. The parity logic is to detect a parity error in a data value stored in the storage structure. The error storage space is to store an indication of a detection of the parity error. The error event generator is to generate an event in response to the indication of the parity error being stored in the error storage space.
    Type: Application
    Filed: December 16, 2011
    Publication date: June 20, 2013
    Inventors: Altug Koker, Shailesh Shah, Aditya Navale, Murali Ramadoss, Satish K. Damaraju
  • Publication number: 20130054992
    Abstract: A method includes detecting a trigger condition, and in response to detecting the trigger condition, reducing a voltage applied to a graphics controller component of a memory controller. The reduction in voltage may cause the voltage to be reduced below a voltage level required to maintain context information in the graphics controller component.
    Type: Application
    Filed: September 27, 2012
    Publication date: February 28, 2013
    Inventors: Eric C. Samson, Aditya Navale
  • Publication number: 20130031333
    Abstract: Methods and apparatus are disclosed for efficient TLB (translation look-aside buffer) shoot-downs for heterogeneous devices sharing virtual memory in a multi-core system. Embodiments of an apparatus for efficient TLB shoot-downs may include a TLB to store virtual address translation entries, and a memory management unit, coupled with the TLB, to maintain PASID (process address space identifier) state entries corresponding to the virtual address translation entries. The PASID state entries may include an active reference state and a lazy-invalidation state. The memory management unit may perform atomic modification of PASID state entries responsive to receiving PASID state update requests from devices in the multi-core system and read the lazy-invalidation state of the PASID state entries. The memory management unit may send PASID state update responses to the devices to synchronize TLB entries prior to activation responsive to the respective lazy-invalidation state.
    Type: Application
    Filed: July 26, 2011
    Publication date: January 31, 2013
    Inventors: Rajesh M. Sankaran, Altug Koker, Philip R. Lantz, Asit K. Mallick, James B. Crossland, Aditya Navale, Gilbert Neiger, Andrew V. Anderson
  • Patent number: 8314806
    Abstract: A controller is described that includes wiring to transport notification that a FIFO that holds data to be used to display content on a display has reached a threshold. The controller also includes first control circuitry to turn on a phase locked loop (PLL) circuit to cause logic circuitry within the controller downstream from the PLL to begin to receive a first clock in response to the notification. The logic circuitry is to transport data read from a memory toward the FIFO. The controller also includes second control circuitry to cause the memory to use a second clock provided by the controller in response to the notification.
    Type: Grant
    Filed: April 13, 2006
    Date of Patent: November 20, 2012
    Assignee: Intel Corporation
    Inventors: Eric Samson, Aditya Navale, Todd Witter
  • Patent number: 8301927
    Abstract: A method includes detecting a trigger condition, and in response to detecting the trigger condition, reducing a voltage applied to a graphics controller component of a memory controller. The reduction in voltage may cause the voltage to be reduced below a voltage level required to maintain context information in the graphics controller component.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: October 30, 2012
    Assignee: Intel Corporation
    Inventors: Eric C. Samson, Aditya Navale
  • Patent number: 8243085
    Abstract: A novel graphics system including workload detection software is disclosed. The novel graphics system increases the voltage and frequency of the graphics hardware in an integrated graphics chipset, depending on operations performed by the hardware, for either a performance advantage or a power savings advantage.
    Type: Grant
    Filed: December 30, 2007
    Date of Patent: August 14, 2012
    Assignee: Intel Corporation
    Inventors: Aditya Navale, Eric C. Samson
  • Publication number: 20120139927
    Abstract: A method and apparatus for creating, updating, and using guest physical address (GPA) to host physical address (HPA) shadow translation tables for translating GPAs of graphics data direct memory access (DMA) requests of a computing environment implementing a virtual machine monitor to support virtual machines. The requests may be sent through a render or display path of the computing environment from one or more virtual machines, transparently with respect to the virtual machine monitor. The creating, updating, and using may be performed by a memory controller detecting entries sent to existing global and page directory tables, forking off shadow table entries from the detected entries, and translating GPAs to HPAs for the shadow table entries.
    Type: Application
    Filed: February 9, 2012
    Publication date: June 7, 2012
    Inventors: Balaji Vembu, Aditya Navale, Wishwesh A. Gandhi
  • Patent number: 8154555
    Abstract: A method and apparatus for creating, updating, and using guest physical address (GPA) to host physical address (HPA) shadow translation tables for translating GPAs of graphics data direct memory access (DMA) requests of a computing environment implementing a virtual machine monitor to support virtual machines. The requests may be sent through a render or display path of the computing environment from one or more virtual machines, transparently with respect to the virtual machine monitor. The creating, updating, and using may be performed by a memory controller detecting entries sent to existing global and page directory tables, forking off shadow table entries from the detected entries, and translating GPAs to HPAs for the shadow table entries.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: April 10, 2012
    Assignee: Intel Corporation
    Inventors: Balaji Vembu, Aditya Navale, Wishwesh Gandhi
  • Publication number: 20110320844
    Abstract: A method includes detecting a trigger condition, and in response to detecting the trigger condition, reducing a voltage applied to a graphics controller component of a memory controller. The reduction in voltage may cause the voltage to be reduced below a voltage level required to maintain context information in the graphics controller component.
    Type: Application
    Filed: September 12, 2011
    Publication date: December 29, 2011
    Inventors: Eric C. Samson, Aditya Navale
  • Patent number: 8037334
    Abstract: A method includes detecting a trigger condition, and in response to detecting the trigger condition, reducing a voltage applied to a graphics controller component of a memory controller. The reduction in voltage may cause the voltage to be reduced below a voltage level required to maintain context information in the graphics controller component.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: October 11, 2011
    Assignee: Intel Corporation
    Inventors: Eric C. Samson, Aditya Navale
  • Publication number: 20110037770
    Abstract: A method and apparatus for creating, updating, and using guest physical address (GPA) to host physical address (HPA) shadow translation tables for translating GPAs of graphics data direct memory access (DMA) requests of a computing environment implementing a virtual machine monitor to support virtual machines. The requests may be sent through a render or display path of the computing environment from one or more virtual machines, transparently with respect to the virtual machine monitor. The creating, updating, and using may be performed by a memory controller detecting entries sent to existing global and page directory tables, forking off shadow table entries from the detected entries, and translating GPAs to HPAs for the shadow table entries.
    Type: Application
    Filed: October 26, 2010
    Publication date: February 17, 2011
    Inventors: Balaji Vembu, Aditya Navale, Wishwesh A. Gandhi