Abstract: Embodiments of the present invention provide channel estimation for multi-level memories using pilot signals. A memory apparatus includes a memory block comprising a plurality of memory cells and adapted to operate with at least two levels of signals for writing data into and reading data from the memory cells. At least two memory cells are employed as reference cells to output a plurality of pilot signals. The memory apparatus also includes a channel block operatively coupled to the memory block, and adapted to facilitate the writing and reading of data into and from the memory cells. The channel block is also adapted to receive the pilot signals and determine one or more disturbance parameters based at least in part on the pilot signals and to compensate the read back signals based at least in part on the determined one or more disturbance parameters during said reading of data from the memory cells. Other embodiments may be described and claimed.

Abstract: A solid state non-volatile memory unit. The memory unit includes a multi-level solid state non-volatile memory array adapted to store data characterized by a first number of digital levels. The memory unit also includes an analog-to-digital converter having an input and an output. The input of the analog-to-digital converter is adapted to receive data from the multi-level solid state non-volatile memory array. The output of the analog-to-digital converter is adapted to output a digital signal characterized by a second number of digital levels greater than the first number of digital levels.

Abstract: In a communication system, a signal transmission apparatus includes an encoder for encoding an information vector into a low density parity check (LDPC) codeword with an LDPC coding scheme, and a puncturer for puncturing the LDPC codeword according to a coding rate using a puncturing scheme. A signal reception apparatus includes a ‘0’ inserter for inserting ‘0’ symbols in a received signal according to a coding rate used in a signal transmission apparatus, and a decoder for decoding the ‘0’ symbol-inserted signal with a decoding scheme corresponding to a low density parity check (LDPC) coding scheme used in the signal transmission apparatus, thereby detecting an information vector.

Abstract: A method and system for providing protection of multiple communication sessions using the bandwidth resources on the order of those required to protect a single communication session. This is facilitated through the use of network coding on a protection cycle. Transmissions from all connections are coded together using network coding and transmitted in two different directions on a cycle, so that the signal can be recovered by the receiver in two ways: on the working path, and on the protection (cycle) path.

Abstract: A solid state non-volatile memory unit. The memory unit includes a multi-level solid state non-volatile memory array adapted to store data characterized by a first number of digital levels. The memory unit also includes an analog-to-digital converter having an input and an output. The input of the analog-to-digital converter is adapted to receive data from the multi-level solid state non-volatile memory array. The output of the analog-to-digital converter is adapted to output a digital signal characterized by a second number of digital levels greater than the first number of digital levels.

Abstract: A MIMO transmitter comprises a scrambler; an encoder parser responsive to the scrambler; a forward error correction encoder responsive to the encoder parser, wherein the encoder applies a parity check matrix derived from a base matrix; an interleaver responsive to the forward error correction encoder; a QAM mapping module responsive to the interleaver; an inverse fast Fourier transform module responsive to the QAM mapping module; and an output module responsive to the inverse fast Fourier transform module.

Abstract: Embodiments of the present invention provide channel estimation for multi-level memories using pilot signals. A memory apparatus includes a memory block comprising a plurality of memory cells and adapted to operate with at least two levels of signals for writing data into and reading data from the memory cells. At least two memory cells are employed as reference cells to output a plurality of pilot signals. The memory apparatus also includes a channel block operatively coupled to the memory block, and adapted to facilitate the writing and reading of data into and from the memory cells. The channel block is also adapted to receive the pilot signals and determine one or more disturbance parameters based at least in part on the pilot signals and to compensate the read back signals based at least in part on the determined one or more disturbance parameters during said reading of data from the memory cells. Other embodiments may be described and claimed.

Abstract: Embodiments of the present invention provide multi-level signal memory with LDPC and interleaving. Thus, various embodiments of the present invention provide a memory apparatus that includes a memory block comprising a plurality of memory cells, each memory cell adapted to operate with multi-level signals. Such a memory apparatus also includes a low density parity check (LDPC) coder to LDPC code data values to be written into the memory cells and an interleaver adapted to apply bit interleaved code modulation (BICM) to the LDPC coded data values to generate BICM coded data values. Other embodiments may be described and claimed.

Abstract: In a communication system, a signal transmission apparatus includes an encoder for encoding an information vector into a low density parity check (LDPC) codeword with an LDPC coding scheme, and a puncturer for puncturing the LDPC codeword according to a coding rate using a puncturing scheme. A signal reception apparatus includes a ‘0’ inserter for inserting ‘0’ symbols in a received signal according to a coding rate used in a signal transmission apparatus, and a decoder for decoding the ‘0’ symbol-inserted signal with a decoding scheme corresponding to a low density parity check (LDPC) coding scheme used in the signal transmission apparatus, thereby detecting an information vector.

Abstract: A solid state non-volatile memory unit. The memory unit includes a multi-level solid state non-volatile memory array adapted to store data characterized by a first number of digital levels. The memory unit also includes an analog-to-digital converter having an input and an output. The input of the analog-to-digital converter is adapted to receive data from the multi-level solid state non-volatile memory array. The output of the analog-to-digital converter is adapted to output a digital signal characterized by a second number of digital levels greater than the first number of digital levels.