Patents by Inventor Adolf Koller
Adolf Koller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8993372Abstract: Exemplary embodiments of a method for producing a semiconductor component having a polycrystalline semiconductor body region are disclosed, wherein the polycrystalline semiconductor body region is produced between the first and second surfaces of the semiconductor body in a semiconductor component section, wherein an electromagnetic radiation having a wavelength of at least 1064 nm is introduced into the semiconductor body in a manner focused onto a position in the semiconductor component section of the semiconductor body and wherein the power density of the radiation at the position is less than 1×108 W/cm2.Type: GrantFiled: February 28, 2012Date of Patent: March 31, 2015Assignee: Infineon Technologies Austria AGInventors: Manfred Schneegans, Carsten Ahrens, Adolf Koller, Gerald Lackner, Anton Mauder, Hans-Joachim Schulze
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Publication number: 20140338827Abstract: Methods and apparatuses are provided where a parting agent is applied to at least one portion of a substrate. The at least one portion of the substrate is removed from a carrier.Type: ApplicationFiled: May 15, 2013Publication date: November 20, 2014Inventors: Adolf Koller, Franco Mariani, Katharina Umminger
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Patent number: 8883565Abstract: In accordance with an embodiment of the present invention, a semiconductor device is manufactured by arranging a plurality of semiconductor devices on a frame with an adhesive foil. The plurality of semiconductor devices is attached to the adhesive foil. The plurality of semiconductor devices is removed from the frame with the adhesive foil using a carbon dioxide snow jet and/or a laser process.Type: GrantFiled: October 4, 2011Date of Patent: November 11, 2014Assignee: Infineon Technologies AGInventors: Mathias Vaupel, Sebastian Bernrieder, Adolf Koller, Stefan Martens
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Publication number: 20140329373Abstract: A method of dicing a semiconductor wafer includes forming a layer stack on a first main surface of a substrate. The layer stack and a portion of the substrate are etched according to a pattern defining an intended dicing location to obtain a trench structure. The substrate is irradiated with a laser beam to locally modify the substrate between a bottom of the trench structure and a second main surface of the substrate opposite to the first main surface.Type: ApplicationFiled: July 15, 2014Publication date: November 6, 2014Inventors: Giuseppe Miccoli, Adolf Koller, Jayachandran Bhaskaran
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Publication number: 20140284771Abstract: A method for manufacturing a plurality of chips comprises the step of providing a wafer comprising a plurality of chip areas separated by one or more dicing lines, wherein the chip areas are arranged on a first main surface, the step of providing a laser absorption layer on a second main surface opposite to the first main surface and the step of providing a backside metal stack on the laser absorption layer. After that a laser light is applied to the laser absorption layer along the dicing lines before the chips are singulated along the dicing lines by using stealth dicing.Type: ApplicationFiled: June 4, 2014Publication date: September 25, 2014Inventors: Gunther Mackh, Adolf Koller
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Patent number: 8809120Abstract: A method of dicing a semiconductor wafer includes forming a layer stack on a first main surface of a substrate. The layer stack and a portion of the substrate are etched according to a pattern defining an intended dicing location to obtain a trench structure. The substrate is irradiated with a laser beam to locally modify the substrate between a bottom of the trench structure and a second main surface of the substrate opposite to the first main surface.Type: GrantFiled: February 17, 2011Date of Patent: August 19, 2014Assignee: Infineon Technologies AGInventors: Giuseppe Miccoli, Adolf Koller, Jayachandran Bhaskaran
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Patent number: 8785234Abstract: A method for manufacturing a plurality of chips comprises the step of providing a wafer comprising a plurality of chip areas separated by one or more dicing lines, wherein the chip areas are arranged on a first main surface, the step of providing a laser absorption layer on a second main surface opposite to the first main surface and the step of providing a backside metal stack on the laser absorption layer. After that a laser light is applied to the laser absorption layer along the dicing lines before the chips are singulated along the dicing lines by using stealth dicing.Type: GrantFiled: October 31, 2012Date of Patent: July 22, 2014Assignee: Infineon Technologies AGInventors: Gunther Mackh, Adolf Koller
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Publication number: 20140170836Abstract: A chip includes a dielectric layer and a fill structure in the dielectric layer, wherein the fill structure extends along a dicing edge of the chip, with the fill structure abutting the dicing edge.Type: ApplicationFiled: February 20, 2014Publication date: June 19, 2014Applicant: INFINEON TECHNOLOGIES AGInventors: Gunther Mackh, Gerhard Leschik, Adolf Koller, Harald Seidl
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Publication number: 20140117505Abstract: A method for manufacturing a plurality of chips comprises the step of providing a wafer comprising a plurality of chip areas separated by one or more dicing lines, wherein the chip areas are arranged on a first main surface, the step of providing a laser absorption layer on a second main surface opposite to the first main surface and the step of providing a backside metal stack on the laser absorption layer. After that a laser light is applied to the laser absorption layer along the dicing lines before the chips are singulated along the dicing lines by using stealth dicing.Type: ApplicationFiled: October 31, 2012Publication date: May 1, 2014Applicant: INFINEON TECHNOLOGIES AGInventors: Gunther Mackh, Adolf Koller
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Patent number: 8704338Abstract: A chip includes a dielectric layer and a fill structure in the dielectric layer, wherein the fill structure extends along a dicing edge of the chip, with the fill structure abutting the dicing edge.Type: GrantFiled: September 28, 2011Date of Patent: April 22, 2014Assignee: Infineon Technologies AGInventors: Gunther Mackh, Gerhard Leschik, Adolf Koller, Harald Seidl
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Publication number: 20140099777Abstract: In one embodiment, a method of forming a semiconductor device comprises forming a groove on and/or over a first side of a substrate. A dicing layer is formed from a second side of the substrate using a laser process. The second side is opposite the first side. The dicing layer is disposed under the groove within the substrate. The substrate is singulated through the dicing layer.Type: ApplicationFiled: October 9, 2012Publication date: April 10, 2014Applicant: INFINEON TECHNOLOGIES AGInventors: Gunther Mackh, Maria Heidenblut, Adolf Koller, Anatoly Sotnikov
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Patent number: 8482019Abstract: An electronic light emitting device includes a leadframe, a light emitting diode arranged above a first surface of the leadframe, a semiconductor chip including an electronic circuit to drive the light emitting diode, the semiconductor chip arranged above a second surface of the leadframe opposite to the first surface of the leadframe.Type: GrantFiled: January 28, 2010Date of Patent: July 9, 2013Assignee: Infineon Technologies AGInventor: Adolf Koller
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Publication number: 20130084658Abstract: In accordance with an embodiment of the present invention, a semiconductor device is manufactured by arranging a plurality of semiconductor devices on a frame with an adhesive foil. The plurality of semiconductor devices is attached to the adhesive foil. The plurality of semiconductor devices is removed from the frame with the adhesive foil using a carbon dioxide snow jet and/or a laser process.Type: ApplicationFiled: October 4, 2011Publication date: April 4, 2013Applicant: Infineon Technologies AGInventors: Mathias Vaupel, Sebastian Bernrieder, Adolf Koller, Stefan Martens
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Publication number: 20130075869Abstract: A chip includes a dielectric layer and a fill structure in the dielectric layer, wherein the fill structure extends along a dicing edge of the chip, with the fill structure abutting the dicing edge.Type: ApplicationFiled: September 28, 2011Publication date: March 28, 2013Applicant: Infineon Technologies AGInventors: Gunther Mackh, Gerhard Leschik, Adolf Koller, Harald Seidl
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Patent number: 8323996Abstract: A method of manufacturing a semiconductor device includes attaching a first semiconductor substrate to a support substrate, and thinning the first semiconductor substrate to form a thinned semiconductor layer. The method additionally includes integrating a functional element with the thinned semiconductor layer, and forming at least one through-connect through the thinned semiconductor layer.Type: GrantFiled: March 2, 2009Date of Patent: December 4, 2012Assignee: Infineon Technologies AGInventors: Adolf Koller, Horst Theuss
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Patent number: 8289019Abstract: A sensor including a substrate and magnetic material. The substrate has a main major surface and includes at least two spaced apart ferromagnetic layers. The magnetic material encapsulates the substrate such that the magnetic material is adjacent the main major surface.Type: GrantFiled: February 11, 2009Date of Patent: October 16, 2012Assignee: Infineon Technologies AGInventors: Adolf Koller, Klaus Elian
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Publication number: 20120225544Abstract: Exemplary embodiments of a method for producing a semiconductor component having a polycrystalline semiconductor body region are disclosed, wherein the polycrystalline semiconductor body region is produced between the first and second surfaces of the semiconductor body in a semiconductor component section, wherein an electromagnetic radiation having a wavelength of at least 1064 nm is introduced into the semiconductor body in a manner focused onto a position in the semiconductor component section of the semiconductor body and wherein the power density of the radiation at the position is less than 1×108 W/cm2.Type: ApplicationFiled: February 28, 2012Publication date: September 6, 2012Inventors: Manfred SCHNEEGANS, Carsten AHRENS, Adolf KOLLER, Gerald LACKNER, Anton MAUDER, Hans-Joachim SCHULZE
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Publication number: 20120211748Abstract: A method of dicing a semiconductor wafer includes forming a layer stack on a first main surface of a substrate. The layer stack and a portion of the substrate are etched according to a pattern defining an intended dicing location to obtain a trench structure. The substrate is irradiated with a laser beam to locally modify the substrate between a bottom of the trench structure and a second main surface of the substrate opposite to the first main surface.Type: ApplicationFiled: February 17, 2011Publication date: August 23, 2012Applicant: Infineon Technologies AGInventors: Giuseppe Miccoli, Adolf Koller, Jayachandran Bhaskaran
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Patent number: 8207018Abstract: A semiconductor package is disclosed. One embodiment provides a semiconductor package singulated from a wafer includes a chip defining an active surface, a back side opposite the active surface, and peripheral sides extending between the active surface and the back side; a contact pad disposed on the active surface; and a metallization layer extending from the contact pad onto a portion of the peripheral sides of the chip.Type: GrantFiled: October 13, 2010Date of Patent: June 26, 2012Assignee: Infineon Technologies AGInventors: Horst Theuss, Adolf Koller
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Patent number: 8164173Abstract: A panel has a baseplate with an upper first metallic layer and a multiplicity of a vertical semiconductor components. The vertical semiconductor components in each case have a first side with a first load electrode and a control electrode and an opposite second side with a second load electrode. The second side of the semiconductor components is in each case mounted on the metallic layer of the baseplate. The semiconductor components are arranged in such a way that edge sides of adjacent semiconductor components are separated from one another. A second metallic layer is arranged in separating regions between the semiconductor components.Type: GrantFiled: July 1, 2010Date of Patent: April 24, 2012Assignee: Infineon Technologies AGInventors: Adolf Koller, Horst Theuss, Ralf Otremba, Josef Hoeglauer, Helmut Strack, Reinhard Ploss