Abstract: A Field Effect Transistor (FET) having a source, drain, and gate disposed laterally along a surface of a semiconductor and a field plate structure: having one end connected to the source; and having a second end disposed between the gate and the drain and separated from the drain by a gap. A dielectric structure is disposed over the semiconductor, having: a first portion disposed under the second end of the field plate structure; and, a second, thinner portion under the gap.

Abstract: Apparatus and method for heating a wafer having semiconductor material. The apparatus includes: a chamber, a source of radiant heat; a source of gas; and a susceptor disposed in the chamber to receive and absorb heat radiated by the source of radiant heat; the susceptor having an opening therein to allow a flow of gas to pass from the source of gas to pass through an interior region of the susceptor and over the wafer.

Abstract: A Field Effect Transistor (FET) having a source, drain, and gate disposed laterally along a surface of a semiconductor and a field plate structure: having one end connected to the source; and having a second end disposed between the gate and the drain and separated from the drain by a gap. A dielectric structure is disposed over the semiconductor, having: a first portion disposed under the second end of the field plate structure; and, a second, thinner portion under the gap.

Abstract: A Field Effect Transistor (FET) having a source, drain, and gate disposed laterally along a surface of a semiconductor and a field plate structure: having one end connected to the source; and having a second end disposed between the gate and the drain and separated from the drain by a gap. A dielectric structure is disposed over the semiconductor, having: a first portion disposed under the second end of the field plate structure; and, a second, thinner portion under the gap.

Abstract: A stack of layers providing an ohmic contact with the semiconductor, a lower metal layer of the stack is disposed in direct contact with the semiconductor; and a radiation absorption control layer disposed over the lower layer for controlling an amount of the radiant energy to be absorbed in the radiation absorption control layer during exposure of the stack to the radiation during a process used to alloy the stack with the semiconductor to form the ohmic contact.

Abstract: A stack of layers providing an ohmic contact with the semiconductor, a lower metal layer of the stack is disposed in direct contact with the semiconductor; and a radiation absorption control layer disposed over the lower layer for controlling an amount of the radiant energy to be absorbed in the radiation absorption control layer during exposure of the stack to the radiation during a process used to alloy the stack with the semiconductor to form the ohmic contact.

Abstract: A Field Effect Transistor (FET) having a source, drain, and gate disposed laterally along a surface of a semiconductor and a field plate structure: having one end connected to the source; and having a second end disposed between the gate and the drain and separated from the drain by a gap. A dielectric structure is disposed over the semiconductor, having: a first portion disposed under the second end of the field plate structure; and, a second, thinner portion under the gap.

Abstract: A method and structure, the structure having a substrate, an active device in an active device semiconductor region; of the substrate, a microwave transmission line, on the substrate, electrically connected to the active device, and microwave energy absorbing “dummy” fill elements on the substrate. The method includes providing a structure having a substrate, an active device region on a surface of the structure, an ohmic contact material on the active device region, and a plurality of “dummy” fill elements on the surface to provide uniform heating of the substrate during a rapid thermal anneal process, the ohmic contact material and the “dummy” fill elements having the same radiant energy reflectivity. The rapid thermal anneal processing forms an ohmic contact between an ohmic contact material and the active device region and simultaneously converts the “dummy” fill elements into microwave lossy “dummy” fill elements.

Abstract: A semiconductor structure having a T-shaped electrode. The electrode has a top portion and a narrower stem portion extending from the top portion to a surface of a substrate. A solid dielectric layer has side portions juxtaposed and abutting sidewalls of a lower portion of the stem of electrode. A bottom surface of the top portion is spaced from an upper surface portion by a non-solid dielectric, such as air.

Abstract: A method and structure, the structure having a substrate, an active device in an active device semiconductor region; of the substrate, a microwave transmission line, on the substrate, electrically connected to the active device, and microwave energy absorbing “dummy” fill elements on the substrate. The method includes providing a structure having a substrate, an active device region on a surface of the structure, an ohmic contact material on the active device region, and a plurality of “dummy” fill elements on the surface to provide uniform heating of the substrate during a rapid thermal anneal process, the ohmic contact material and the “dummy” fill elements having the same radiant energy reflectivity. The rapid thermal anneal processing forms an ohmic contact between an ohmic contact material and the active device region and simultaneously converts the “dummy” fill elements into microwave lossy “dummy” fill elements.

Abstract: A structure having: a substrate; a passivation layer disposed over a surface of substrate; an etch stop layer disposed on the passivation layer; resistor comprising tantalum nitride, disposed on the etch stop layer. The etch stop layer has an etch rate at least 100 times slower than an etch rate of the tantalum nitride to a predetermined etchant.

Abstract: A semiconductor structure having a T-shaped electrode. The electrode has a top portion and a narrower stem portion extending from the top portion to a surface of a substrate. A solid dielectric layer has side portions juxtaposed and abutting sidewalls of a lower portion of the stem of electrode. A bottom surface of the top portion is spaced from an upper surface portion by a non-solid dielectric, such as air.

Abstract: A method for forming a semiconductor structure having a transistor device with a control electrode for controlling a flow of carriers between a first electrode and a second electrode. A passivation layer is deposited over the first electrode, the second electrode and the control electrode. An etch stop layer is deposited on the passivation layer over the control electrode. The etch stop layer includes the etch stop layer comprising: a first etch stop layer on the passivation layer, a buffer layer on the first etch stop layer, and a second etch stop layer on the buffer layer. A dielectric layer is formed over the etch stop layer. A window is etched through a selected region in the dielectric layer over the control electrode, to expose a portion of the etch stop layer disposed over the control electrode. A metal layer is formed on a portion of the etch stop layer and the dielectric layer is also formed on the metal layer.

Abstract: A method for forming a semiconductor structure having a transistor device with a control electrode for controlling a flow of carriers between a first electrode and a second electrode. A passivation layer is deposited over the first electrode, the second electrode and the control electrode. An etch stop layer is deposited on the passivation layer over the control electrode. The etch stop layer includes the etch stop layer comprising: a first etch stop layer on the passivation layer, a buffer layer on the first etch stop layer, and a second etch stop layer on the buffer layer. A dielectric layer is formed over the etch stop layer. A window is etched through a selected region in the dielectric layer over the control electrode, to expose a portion of the etch stop layer disposed over the control electrode. A metal layer is formed on a portion of the etch stop layer and the dielectric layer is also formed on the metal layer.

Abstract: Films of III-nitride for semiconductor device growth are planarized using an etch-back method. The method includes coating a III-nitride surface having surface roughness features in the micron range with a sacrificial planarization material such as an appropriately chosen photoresist. The sacrificial planarization material is then etched together with the III-nitride roughness features using dry etch methods such as inductively coupled plasma reactive ion etching. By closely matching the etch rates of the sacrificial planarization material and the III-nitride material, a planarized III-nitride surface is achieved. The etch-back process together with a high temperature annealing process yields a planarized III-nitride surface with surface roughness features reduced to the nm range. Planarized III-nitride, e.g., GaN, substrates and devices containing them are also provided.

Abstract: A semiconductor structure having a T-shaped electrode. The electrode has a top portion and a narrower stem portion extending from the top portion to a surface of a substrate. A solid dielectric layer has side portions juxtaposed and abutting sidewalls of a lower portion of the stem of electrode. A bottom surface of the top portion is spaced from an upper surface portion by a non-solid, dielectric, such as air.

Abstract: A method for forming a semiconductor structure having a transistor device with a control electrode for controlling a flow of carriers between a first electrode and a second electrode. A passivation layer is deposited over the first electrode, the second electrode and the control electrode. An etch stop layer is deposited on the passivation layer over the control electrode. A dielectric layer is formed over the etch stop layer. A window is etched through a selected region in the dielectric layer over the control electrode, to expose a portion of the etch stop layer disposed over the control electrode. A metal layer is formed on a portion of the etch stop layer and the dielectric layer is also formed on the metal layer. A second metal layer is deposited on the portion of the dielectric layer formed on the first mentioned metal layer.

Abstract: A method for forming a semiconductor structure having a transistor device with a control electrode for controlling a flow of carriers between a first electrode and a second electrode. A passivation layer is deposited over the first electrode, the second electrode and the control electrode. An etch stop layer is deposited on the passivation layer over the control electrode. A dielectric layer is formed over the etch stop layer. A window is etched through a selected region in the dielectric layer over the control electrode, to expose a portion of the etch stop layer disposed over the control electrode. A metal layer is formed on a portion of the etch stop layer and the dielectric layer is also formed on the metal layer. A second metal layer is deposited on the portion of the dielectric layer formed on the first mentioned metal layer.

Abstract: Films of III-nitride for semiconductor device growth are planarized using an etch-back method. The method includes coating a III-nitride surface having surface roughness features in the micron range with a sacrificial planarization material such as an appropriately chosen photoresist. The sacrificial planarization material is then etched together with the III-nitride roughness features using dry etch methods such as inductively coupled plasma reactive ion etching. By closely matching the etch rates of the sacrificial planarization material and the III-nitride material, a planarized III-nitride surface is achieved. The etch-back process together with a high temperature annealing process yields a planarized III-nitride surface with surface roughness features reduced to the nm range. Planarized III-nitride, e.g., GaN, substrates and devices containing them are also provided.

Abstract: Films of III-nitride for semiconductor device growth are planarized using an etch-back method. The method includes coating a III-nitride surface having surface roughness features in the micron range with a sacrificial planarization material such as an appropriately chose photoresist. The sacrificial planarization material is then etched together with the III-nitride roughness features using dry etch methods such as inductively coupled plasma reactive ion etching. By closely matching the etch rates of the sacrificial planarization material and the III-nitride material, a planarized III-nitride surface is achieved. The etch-back process together with a high temperature annealing process yields a planarize III-nitride surface with surface roughness features reduced to the nm range. Planarized III-nitride, e.g., GaN, substrates and devices containing them are also provided.