MONOLITHIC INTEGRATED CIRCUIT (MMIC) STRUCTURE HAVING COMPOSITE ETCH STOP LAYER AND METHOD FOR FORMING SUCH STRUCTURE
A method for forming a semiconductor structure having a transistor device with a control electrode for controlling a flow of carriers between a first electrode and a second electrode. A passivation layer is deposited over the first electrode, the second electrode and the control electrode. An etch stop layer is deposited on the passivation layer over the control electrode. The etch stop layer includes the etch stop layer comprising: a first etch stop layer on the passivation layer, a buffer layer on the first etch stop layer, and a second etch stop layer on the buffer layer. A dielectric layer is formed over the etch stop layer. A window is etched through a selected region in the dielectric layer over the control electrode, to expose a portion of the etch stop layer disposed over the control electrode. A metal layer is formed on a portion of the etch stop layer and the dielectric layer is also formed on the metal layer. A second metal layer is deposited on the portion of the dielectric layer formed on the first mentioned metal layer.
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This disclosure relates generally to a Monolithic Integrated Circuit (MMIC) Structure and to a method for selectively etching a dielectric layer using an underling etch stop layer to protect an underling active device passivation layer.
BACKGROUND AND SUMMARYAs is known in the art, as monolithic microwave integrated circuits (MMICs) are designed to operate at ever higher frequencies, the effects of dielectric loading on various MMIC conduction paths (including gates and transmission lines) becomes more pronounced. The minimization of such loading is critical to achieving the desired gain performance.
As is also known in the art, plasma enhanced chemical vapor deposition (PECVD) is widely used for the deposition of silicon nitride, which may act as a passivation layer to passivate components, or act as a capacitor dielectric. This deposition technique however, coats regions of the MMIC where the presence of additional dielectric is not desired and adversely impacts device performance at the higher frequencies.
As described in co-pending patent application, Ser. No. 13/849,858, filed Mar. 25, 2013, published in U.S. Patent Application Publication 2014/0284661, published Sep. 25, 2014, assigned to the same assignee as the present patent application, a method was disclosed for forming a semiconductor structure, the entire subject matter thereof being incorporated herein by reference. The method included: providing a semiconductor layer with a transistor device having a control electrode for controlling a flow of carriers between a first electrode and a second electrode; depositing a passivation layer over the first electrode, the second electrode and the control electrode; depositing an etch stop layer on the passivation layer, such etch stop layer being disposed over the control electrode; forming a dielectric layer over the etch stop layer; and etching a window through a selected region in the dielectric layer over the control electrode, to expose a portion of the etch stop layer disposed over the control electrode.
In forming such structure it was discovered that chemicals used in the photolithographic processing effected the etch stop layer.
In accordance with this disclosure, the etch stop layer is formed as a composite structure, comprising: a first etch stop layer on the passivation layer, a buffer layer on the first etch stop layer, and a second etch stop layer on the buffer layer. With such an arrangement, chemicals used in the photolithographic processing while effecting the second etch stop layer are prevented from effecting the first etch stop layer by the buffer layer.
More particularly, it was found that the etch stop layer described in the above referenced U.S. Patent Application Publication 2014/0284661 was subject to attack from other commonly used process chemicals in standard MMIC fabrication such as ammonia and photoresist developer. Employing a buffer, such as, for example, a silicon dioxide interlayer, effectively creates a double-selective etch-stop layer that survives typical MMIC fabrication processing up to the point where etch-back is required. Post etch-back, it has been found that the residual etch stop material can be removed by timed exposure to ammonia since ammonia acts as a highly selective etchant to Atomic Layer Deposition (ALD) deposited aluminum oxide to PECVD nitride. This removal mitigates impact to RF performance of any residual dielectric associated with the etch-stop layer.
In one embodiment, the first etch stop layer is aluminum oxide.
In one embodiment the buffer layer is silicon dioxide;
In one embodiment, the second etch stop layer is aluminum oxide.
In one embodiment, the transistor device is a field effect transistor.
In one embodiment, the semiconductor layer is a semiconductor material.
In one embodiment, the passivation layer is silicon nitride.
In one embodiment, the dielectric layer is silicon nitride.
In one embodiment, the dielectric layer is Plasma Enhanced Chemical Vapor Deposited (PECVD) silicon nitride
In one embodiment, the first etch stop layer is an atomic layer deposited (ALD) layer.
In one embodiment, the second etch stop layer is an atomic layer deposited (ALD) layer.
The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims.
Like reference symbols in the various drawings indicate like elements.
DETAILED DESCRIPTIONReferring now to
Next, referring to
Next, referring to
Next, referring to
Next, referring to
Referring now also to
Next, exposed portions of the second etch stop layer 26c of ALD aluminum oxide layer are removed to clean the top surface of the wafer prior to depositing a PECVD silicon nitride layer 40 (
Next, a photoresist layer 42 is deposited and photolithographically processed to have a window 44 formed therein, as shown in
Next, the second level (level 2) metallization process begins by depositing a photoresist layer 50 and pattering the photoresist layer 50 lithographically to have windows 52 formed there-through, as shown in
Next, the aluminum oxide layer 26a is removed from regions unprotected by metal 34 or silicon nitride layer 40, as shown in
It should be noted that the process described above may be modified so that the composite etch stop layer, shown in
A number of embodiments of the disclosure have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the disclosure. For example, the method may be used with bipolar transistors. Accordingly, other embodiments are within the scope of the following claims.
Claims
1. A method for forming a semiconductor structure, comprising
- providing a semiconductor layer with a transistor device having a control electrode for controlling a flow of carriers between a first electrode and a second electrode;
- depositing a passivation layer over the first electrode, the second electrode and the control electrode;
- depositing an etch stop layer on the passivation layer, such etch stop layer being disposed over the control electrode, the etch stop layer comprising: a first etch stop layer on the passivation layer, a buffer layer on the first etch stop layer, and a second etch stop layer on the buffer layer;
- forming a dielectric layer over the etch stop layer; and
- etching a window through a selected region in the dielectric layer over the control electrode, to expose a portion of the etch stop layer disposed over the control electrode.
2. The method recited in claim 1 including:
- forming a metal layer on a portion of the etch stop layer; and
- wherein the dielectric layer is also formed on the metal layer.
3. The method recited in claim 2 including depositing a second metal layer on the portion of the dielectric layer formed on the first mentioned metal layer
4. The method recited in claim 3 wherein the transistor device is a field effect transistor.
5. The method recited in claim 3 wherein the semiconductor layer is a semiconductor material.
6. The method recited in claim 3 wherein the passivation layer is silicon nitride.
7. The method recited in claim 3 wherein the dielectric layer is silicon nitride.
8. The method recited in claim 7 wherein the dielectric layer is Plasma Enhanced Chemical Vapor Deposited (PECVD) silicon nitride
9. The method recited in claim 1 wherein the etch stop layer is an atomic layer deposited (ADD) layer.
10. The method recited in claim 9 wherein the etching comprises using reactive ion etching (RIE) or inductively coupled plasma (ICP) etching and photoresist patterning.
11. The method recited in claim 10 wherein the etching uses sulfur hexafluoride based plasma etchants.
12. A method for forming a semiconductor structure comprising;
- providing a III-V semiconductor layer with source and drain electrodes in ohmic contact with the semiconductor layer and a gate electrode in Schottky contact with the semiconductor layer;
- depositing a passivation layer over the source, drain and gate electrodes,
- depositing an etch stop layer on the passivation layer;
- forming a dielectric layer over the etch stop layer, the etch stop layer comprising: a first etch stop layer on the passivation layer, a buffer layer on the first etch stop layer, and a second etch stop layer on the buffer layer;
- forming a window in the dielectric layer exposing a portion of the etch stop layer deposed over the gate electrode.
13. A semiconductor structure comprising;
- a III-V semiconductor layer;
- source and drain electrodes in ohmic contact with the semiconductor layer;
- a gate electrode in Schottky contact with the semiconductor layer;
- a passivation layer disposed over the source, drain and gate electrodes,
- an etch stop layer disposed on the passivation layer, the etch stop layer comprising: a first etch stop layer on the passivation layer, a buffer layer on the first etch stop layer, and a second etch stop layer on the buffer layer;
- a dielectric layer disposed on a first portion of the etch stop layer, the dielectric layer having a window therein, such window exposing a second portion of the etch stop layer.
14. The semiconductor structure recited in claim 13 wherein the etch stop layer is disposed over portions of the source and drain electrodes.
15. The method recited in claim 1 wherein the etch stop layer is deposited over the first electrode and the second electrode.
16. The method recited in claim 15 wherein the etch stop layer is deposited over the source electrode and drain electrode.
17. A method for forming a semiconductor structure, comprising
- providing a semiconductor layer with a transistor device having a control electrode for controlling a flow of carriers between a first electrode and a second electrode;
- depositing a passivation layer over the first electrode, the second electrode and the control electrode;
- depositing an etch stop layer on the passivation layer, such etch stop layer being disposed over the control electrode, the etch stop layer comprising: a first etch stop layer on the passivation layer, a buffer layer on the first etch stop layer, and a second etch stop layer on the buffer layer;
- forming a dielectric layer over the etch stop layer;
- etching a window through a selected region in the dielectric layer to expose the entire gate electrode and extends from the first electrode to the second electrodes.
18. The method recited in claim 1 wherein the portion of the etch stop layer disposed over the control electrode is removed.
19. The method recited in claim 18 wherein the portion of the etch stop layer disposed over the control electrode removal includes using an ammonia wash.
Type: Application
Filed: Apr 10, 2015
Publication Date: Oct 13, 2016
Applicant: Raytheon Company (Waltham, MA)
Inventor: Adrian D. Williams (Methuen, MA)
Application Number: 14/683,812