Abstract: A semiconductor die includes: a semiconductor substrate having an active region and an edge termination region that separates the active region from an edge of the semiconductor substrate; a plurality of transistor cells formed in the active region; a structured power metallization above the semiconductor substrate and including a gate pad and a gate runner that extends from the gate pad along one or more but not all sides of the semiconductor die above the edge termination region, the gate runner electrically connecting the gate pad to gate electrodes of the transistor cells; and a tungsten runner that follows the gate runner and contacts an underside of the gate runner. The tungsten runner is present above the edge termination region along each side of the semiconductor die that is at least partly devoid of the gate runner. A Method of producing the semiconductor die is also described.

Abstract: A method of manufacturing a power device includes: etching a trench in a semiconductor body; forming at least a first layer of dielectric material in the trench; forming a first field electrode structure on the at least one first layer of dielectric material and in the trench; forming at least one second layer of dielectric material on the first electrode structure and in the trench; and forming a second field electrode structure on the at least one second layer of dielectric material and in the trench.

Abstract: The disclosure relates to a power device, having a channel region, a gate region formed aside the channel region, for controlling a channel formation, a drift region formed vertically below the channel region, a field electrode formed in a field electrode trench extending vertically into the drift region, wherein the field electrode comprises a first and a second field electrode structure, the first field electrode structure capacitively coupling to a first section of the drift region and the second field electrode structure capacitively coupling to a second section of the drift region, arranged vertically above the first section, the first and the second field electrode structure formed with a vertical overlap and adapted to balance a capacitive coupling between the first and the second field electrode structure and between the field electrode and the drift region.

Abstract: An electronic circuit and a method are disclosed. The electronic circuit includes: a first transistor device having a load path between a first load path node and a second load path node; and a clamping circuit connected to the load path of the first transistor device. The clamping circuit includes: a second transistor device having a load path connected in parallel with the load path of the first transistor device, and a control node; and a drive circuit configured to drive the second transistor device. The drive circuit includes a clamping element and a resistor connected in series between the first and second load path nodes of the first transistor device. The drive circuit is configured to drive the second transistor device dependent on a voltage across the resistor. The first transistor device and the clamping circuit are integrated in a same semiconductor die.

Abstract: An electronic circuit and a method are disclosed. The electronic circuit includes: a first transistor device having a load path between a first load path node and a second load path node; and a clamping circuit connected to the load path of the first transistor device. The clamping circuit includes: a second transistor device having a load path connected in parallel with the load path of the first transistor device, and a control node; and a drive circuit configured to drive the second transistor device. The drive circuit includes a clamping element and a resistor connected in series between the first and second load path nodes of the first transistor device. The drive circuit is configured to drive the second transistor device dependent on a voltage across the resistor. The first transistor device and the clamping circuit are integrated in a same semiconductor die.

Abstract: The application relates to a semiconductor die including a device in an active area of the die. The device includes a field electrode region formed in a field electrode trench extending vertically into a semiconductor body. The field electrode region includes a first and a second field electrode stacked vertically above each other in the field electrode trench. An edge termination structure laterally between the active area and a lateral edge region of the die includes a first and a second shield electrode arranged laterally consecutive between the active area and the lateral edge region to stepwise decrease an electrical potential between the edge region and the active area.

Abstract: A semiconductor device includes: a semiconductor substrate; a drift zone of a first conductivity type in the semiconductor substrate; an array of interconnected gate trenches extending from a first surface of the semiconductor substrate into the drift zone; a plurality of semiconductor mesas delimited by the array of interconnected gate trenches; a plurality of needle-shaped field plate trenches extending from the first surface into the plurality of semiconductor mesas; in the plurality of semiconductor mesas, a source region of the first conductivity type and a body region of a second conductivity type separating the source region from the drift zone; and a current spreading region of the first conductivity type at the bottom of the gate trenches and having a higher average doping concentration than the drift zone. Methods of producing the semiconductor device are also described.

Abstract: The disclosure relates to a semiconductor die with a transistor device, which has a channel region formed in a semiconductor body, a gate region aside the channel region, for controlling a channel formation, a drift region formed in the semiconductor body, and a field electrode in a field electrode trench, which extends from a frontside of the semiconductor body vertically into the drift region, wherein an insulating layer is formed on the frontside of the semiconductor body and a frontside metallization is formed on the insulating layer, and wherein a capacitor electrode is formed in the insulating layer, which is conductively connected to at least a portion of the field electrode.

Abstract: A semiconductor arrangement is disclosed. The semiconductor arrangement includes: a semiconductor body and a temperature sensor (TES) integrated in the semiconductor body. The TES includes: a first semiconductor region of a first doping type arranged, in a vertical direction of the semiconductor body, between a second semiconductor region of a second doping type and a third semiconductor of the second doping type, and a contact plug ohmically connecting the first semiconductor region and the second semiconductor region. The first semiconductor region includes a base region section spaced apart from the contact plug in a first lateral direction of the semiconductor body and a resistor section arranged between the base region section and the contact plug. The resistor section is implemented such that an ohmic resistance of the resistor section between the base region section and the first semiconductor region is at least 1 M?.

Abstract: An electronic circuit and a method are disclosed. The electronic circuit includes: a first transistor device having a load path between a first load path node and a second load path node; and a clamping circuit connected to the load path of the first transistor device. The clamping circuit includes: a second transistor device having a load path connected in parallel with the load path of the first transistor device, and a control node; and a drive circuit configured to drive the second transistor device. The drive circuit includes a clamping element and a resistor connected in series between the first and second load path nodes of the first transistor device. The drive circuit is configured to drive the second transistor device dependent on a voltage across the resistor. The first transistor device and the clamping circuit are integrated in a same semiconductor die.

Abstract: A semiconductor die includes: a semiconductor substrate having an active region and an edge termination region that separates the active region from an edge of the semiconductor substrate; a plurality of transistor cells formed in the active region; a structured power metallization above the semiconductor substrate and including a gate pad and a gate runner that extends from the gate pad along one or more but not all sides of the semiconductor die above the edge termination region, the gate runner electrically connecting the gate pad to gate electrodes of the transistor cells; and a tungsten runner that follows the gate runner and contacts an underside of the gate runner. The tungsten runner is present above the edge termination region along each side of the semiconductor die that is at least partly devoid of the gate runner. A Method of producing the semiconductor die is also described.

Abstract: A semiconductor device includes: a semiconductor substrate; a drift zone of a first conductivity type in the semiconductor substrate; an array of interconnected gate trenches extending from a first surface of the semiconductor substrate into the drift zone; a plurality of semiconductor mesas delimited by the array of interconnected gate trenches; a plurality of needle-shaped field plate trenches extending from the first surface into the plurality of semiconductor mesas; in the plurality of semiconductor mesas, a source region of the first conductivity type and a body region of a second conductivity type separating the source region from the drift zone; and a current spreading region of the first conductivity type at the bottom of the gate trenches and having a higher average doping concentration than the drift zone. Methods of producing the semiconductor device are also described.

Abstract: The application relates to a semiconductor die including a device in an active area of the die. The device includes a field electrode region formed in a field electrode trench extending vertically into a semiconductor body. The field electrode region includes a first and a second field electrode stacked vertically above each other in the field electrode trench. An edge termination structure laterally between the active area and a lateral edge region of the die includes a first and a second shield electrode arranged laterally consecutive between the active area and the lateral edge region to stepwise decrease an electrical potential between the edge region and the active area.

Abstract: A semiconductor device includes a semiconductor body having an active area with active transistor cells. Each active transistor cell includes a columnar trench having a field plate and a mesa. An edge termination region that laterally surrounds the active area includes a transition region, an outer termination region, and inactive cells arranged in the transition region and outer termination region. Each inactive cell includes a columnar termination trench having a field plate and a termination mesa including a drift region. In the transition region, the termination mesa includes a body region arranged on the drift region and in the outer termination region the drift region of the termination mesa extends to the first surface. The edge termination region further includes a continuous trench positioned in the outer termination region, that laterally surrounds the columnar termination trenches, and is filled with at least one dielectric material.

Abstract: The disclosure relates to a semiconductor die with a transistor device, which has a channel region formed in a semiconductor body, a gate region aside the channel region, for controlling a channel formation, a drift region formed in the semiconductor body, and a field electrode in a field electrode trench, which extends from a frontside of the semiconductor body vertically into the drift region, wherein an insulating layer is formed on the frontside of the semiconductor body and a frontside metallization is formed on the insulating layer, and wherein a capacitor electrode is formed in the insulating layer, which is conductively connected to at least a portion of the field electrode.

Abstract: The disclosure relates to a power device, having a channel region, a gate region formed aside the channel region, for controlling a channel formation, a drift region formed vertically below the channel region, a field electrode formed in a field electrode trench extending vertically into the drift region, wherein the field electrode comprises a first and a second field electrode structure, the first field electrode structure capacitively coupling to a first section of the drift region and the second field electrode structure capacitively coupling to a second section of the drift region, arranged vertically above the first section, the first and the second field electrode structure formed with a vertical overlap and adapted to balance a capacitive coupling between the first and the second field electrode structure and between the field electrode and the drift region.

Abstract: A semiconductor arrangement is disclosed. The semiconductor arrangement includes: a semiconductor body and a temperature sensor (TES) integrated in the semiconductor body. The TES includes: a first semiconductor region of a first doping type arranged, in a vertical direction of the semiconductor body, between a second semiconductor region of a second doping type and a third semiconductor of the second doping type, and a contact plug ohmically connecting the first semiconductor region and the second semiconductor region. The first semiconductor region includes a base region section spaced apart from the contact plug in a first lateral direction of the semiconductor body and a resistor section arranged between the base region section and the contact plug. The resistor section is implemented such that an ohmic resistance of the resistor section between the base region section and the first semiconductor region is at least 1 M?.

Abstract: A transistor arrangement and an electronic circuit with a transistor arrangement are disclosed. The transistor arrangement includes: drift and drain regions arranged in a semiconductor body and connected to a drain node; at least one load transistor cell having a source region integrated in a first active region of the semiconductor body; at least one sense transistor cell having a source region integrated in a second active region of the semiconductor body; a first source node electrically coupled to the source region of the at least one load transistor cell; a second source node electrically coupled to the source region of the at least one sense transistor cell; and a compensation resistor connected between the source region of the at least one sense transistor cell and the second source node. The compensation resistor is integrated in the semiconductor body and has a resistive conductor which includes a doped semiconductor material.

Abstract: A transistor arrangement and an electronic circuit with a transistor arrangement are disclosed. The transistor arrangement includes: drift and drain regions arranged in a semiconductor body and connected to a drain node; at least one load transistor cell having a source region integrated in a first active region of the semiconductor body; at least one sense transistor cell having a source region integrated in a second active region of the semiconductor body; a first source node electrically coupled to the source region of the at least one load transistor cell; a second source node electrically coupled to the source region of the at least one sense transistor cell; and a compensation resistor connected between the source region of the at least one sense transistor cell and the second source node. The compensation resistor is integrated in the semiconductor body and has a resistive conductor which includes a doped semiconductor material.

Abstract: Disclosed are a transistor device and a method. The transistor device includes a semiconductor body with a first surface, an inner region, and an edge region, a drift region of a first doping type in the inner region and the edge region, a plurality of transistor cells in the inner region, and a termination structure in the edge region. The termination structure includes a recess extending from the first surface in the edge region into the semiconductor body, and a floating compensation region with dopant atoms of a second doping type complementary to the first doping type in the drift region adjacent the recess.