Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes a power device well in a semiconductor substrate, a logic device well in the substrate and spaced apart from the power device well by a separation region of the substrate, and a minority carrier conversion structure including a first doped region of a first conductivity type in the separation region, a second doped region of a second conductivity type in the separation region and a conducting layer connecting the first and second doped regions. The second doped region includes a first part interposed between the first doped region and the power device well and a second part interposed between the first doped region and the logic device well.

Abstract: A semiconductor device comprises a semiconductor substrate doped with dopants of a first type and a vertical transistor composed of one or more transistor cells. Each transistor cell has a first region formed in the substrate and doped with dopants of a second type, and the first regions form first pn-junctions with the surrounding substrate. At least a first well region is formed in the substrate and doped with dopants of a second type to form a second pn-junction with the substrate. The first well region is electrically connected to the first regions of the vertical transistor via a semiconductor switch. The semiconductor device comprises a detection circuit, which is integrated in the substrate and configured to detect whether the first pn-junctions are reverse biased. The switch is opened when the first pn-junctions are reverse biased and the switch is closed when the first pn-junctions are not reverse biased.

Abstract: A semiconductor device comprises semiconductor substrate including vertical transistor and with dopants of a first type. Each transistor cell of transistor has body region formed in substrate and with dopants of second type. The body regions form first pn-junctions with substrate. A first well region is formed in substrate and with dopants of a second type forming a second pn-junction with substrate. Switch connects this first well region to body regions. A second well region is formed in the substrate and with dopants of a second type to form third pn-junction with substrate. Detection circuit is integrated in the second well region and to detect whether the first pn-junctions are reverse biased. The switch connects or disconnects the first well region(s) and the body regions of the transistor cell, and is opened, when the first pn-junctions are reverse biased, and dosed, when the first pn-junctions are not reverse biased.

Abstract: A two-stage protection device for an electronic component protects against transient disturbances. The electronic component may be a semiconductor component, and may include one or multiple transistors and/or an integrated circuit. The protection device is connected to at least a first contact and a second contact of the electronic component, and is disposed essentially in parallel to the component that is to be protected, between the first contact and the second contact. The protection device includes a first stage with at least one diode and a second stage separated from the first stage by a resistor. The second stage includes at least one diode arrangement having two back-to-back disposed diodes which are disposed cathode-to-cathode.

Abstract: A semiconductor device includes a semiconductor material of a first conductivity type, a body region of a second (opposite) conductivity type extending into the semiconductor material from a main surface of the semiconductor material, a source region of the first conductivity type disposed in the body region, and a channel region extending laterally in the body region from the source region along the main surface. A charge compensation region of the second conductivity type can be provided under the body region which extends in a direction parallel to the main surface and terminates prior to a pn-junction between the source and body regions at the main surface, and/or an additional region of the first conductivity type which has at least one peak doping concentration each of which occurs deeper in the semiconductor material from the main surface than a peak doping concentration of the device channel region.

Abstract: A semiconductor device includes an epitaxial layer of semiconductor material of a first conductivity type, a body region of a second (opposite) conductivity type extending into the epitaxial layer from a main surface of the epitaxial layer, a source region of the first conductivity type disposed in the body region, and a channel region extending laterally in the body region from the source region along the main surface. A charge compensation region of the second conductivity type can be provided under the body region which extends in a direction parallel to the main surface and terminates prior to a pn-junction between the source and body regions at the main surface, and/or an additional region of the first conductivity type which has at least one peak doping concentration each of which occurs deeper in the epitaxial layer from the main surface than a peak doping concentration of the device channel region.

Abstract: A semiconductor device includes an epitaxial layer of semiconductor material of a first conductivity type, a body region of a second (opposite) conductivity type extending into the epitaxial layer from a main surface of the epitaxial layer, a source region of the first conductivity type disposed in the body region, and a channel region extending laterally in the body region from the source region along the main surface. A charge compensation region of the second conductivity type can be provided under the body region which extends in a direction parallel to the main surface and terminates prior to a pn-junction between the source and body regions at the main surface, and/or an additional region of the first conductivity type which has at least one peak doping concentration each of which occurs deeper in the epitaxial layer from the main surface than a peak doping concentration of the device channel region.

Abstract: Representative implementations of devices and techniques provide a bandgap reference voltage using at least one polysilicon diode and no silicon diodes. The polysilicon diode is comprised of three portions, a lightly doped portion flanked by a more heavily doped portion on each end.

Abstract: A two-stage protection device for an electronic component protects against transient disturbances. The electronic component may be a semiconductor component, and may include one or multiple transistors and/or an integrated circuit. The protection device is connected to at least a first contact and a second contact of the electronic component, and is disposed essentially in parallel to the component that is to be protected, between the first contact and the second contact. The protection device includes a first stage with at least one diode and a second stage separated from the first stage by a resistor. The second stage includes at least one diode arrangement having two back-to-back disposed diodes which are disposed cathode-to-cathode.

Abstract: A power supply circuit has a first MOSFET having a body region between the source and drain. The body region is connected so as to be at the same potential as the source. Application of a suitable potential to the gate causes the MOSFET to switch to a conductive on state. The power supply circuit also has signal generation circuitry, which generates a signal indicative of a conductive state of the first MOSFET. The signal generation circuitry generates a reference voltage of a predetermined potential difference from the source potential. The power supply circuit further comprises a second MOSFET having a body region connected so as to be at the same potential as the drain of the first MOSFET, and the second gate is connected to receive the reference voltage.

Abstract: A power supply circuit has a first MOSFET having a body region between the source and drain. The body region is connected so as to be at the same potential as the source. Application of a suitable potential to the gate causes the MOSFET to switch to a conductive on state. The power supply circuit also has signal generation circuitry, which generates a signal indicative of a conductive state of the first MOSFET. The signal generation circuitry generates a reference voltage of a predetermined potential difference from the source potential. The power supply circuit further comprises a second MOSFET having a body region connected so as to be at the same potential as the drain of the first MOSFET, and the second gate is connected to receive the reference voltage.

Abstract: A temperature dependent switching circuit comprises a first transistor with a threshold voltage Vth having a negative temperature coefficient. A diode having a forward voltage drop with a negative temperature coefficient coupled with its anode connected to the drain of the first transistor and its cathode connected to the gate of the first transistor. A first resistor is coupled between a power supply terminal and the drain of the first transistor. A low voltage supply is terminal connected to the source of the first transistor. A second resistor is coupled between the gate of the first transistor and the low voltage supply terminal. A switching transistor has its source connected to the low voltage supply terminal and its gate coupled to the drain of the first transistor. The drain of the first transistor provides a voltage with a negative temperature coefficient equal to the sum of the forward voltage drop across the diode and the threshold voltage of the first transistor.

Abstract: A temperature independent low voltage reference circuit comprises a first transistor with a threshold voltage Vth having a negative temperature coefficient. A diode having a forward voltage drop with a negative temperature coefficient coupled with its anode connected to the drain of the first transistor and its cathode connected to the gate of the first transistor. A first resistor coupled between a power supply terminal and the drain of the first transistor. A low voltage supply terminal connected to the source of the first transistor. A second resistor coupled between the gate of the first transistor and the low voltage supply terminal. The drain of the first transistor provides a voltage with a negative temperature coefficient equal to the sum of the forward voltage drop across the diode and the threshold voltage of the first transistor.

Abstract: A temperature independent low voltage reference circuit comprises a first transistor with a threshold voltage Vth having a negative temperature coefficient. A diode having a forward voltage drop with a negative temperature coefficient coupled with its anode connected to the drain of the first transistor and its cathode connected to the gate of the first transistor. A first resistor coupled between a power supply terminal and the drain of the first transistor. A low voltage supply terminal connected to the source of the first transistor. A second resistor coupled between the gate of the first transistor and the low voltage supply terminal. The drain of the first transistor provides a voltage with a negative temperature coefficient equal to the sum of the forward voltage drop across the diode and the threshold voltage of the first transistor.

Abstract: A high side switching circuit, comprising: a switching transistor; a charge pump drive circuit including a circuit for generating an oscillating signal; and a charge pump arranged to provide a gate drive voltage to the switching transistor in response to a control signal; wherein the charge pump is driven by the charge pump drive circuit, and the circuit for generating an oscillating signal comprises: an oscillator having a power supply input and first and second outputs, outputting first and second pulse trains respectively of the same frequency but out of phase such that when the first pulse train is high, the second pulse train is low and when the second pulse train is high, the first pulse train is low; first and second transistors connected in series with the drain of the first transistor connected to a high voltage input relative to the high level of the first and second pulse train pulses, the source of the first transistor connected to the drain of the second transistor, the source of the second trans

Abstract: A semiconductor device (e.g. MOSFET or IGBT) comprises active and termination regions (1,2) formed in a semiconductor substrate (4). The substrate (4) has an upper surface and a termination including a trench (12) extending into the substrate (4) from the upper surface within the termination region (1). Termination trench (12) is at least partly filled with an insulating material (13) which extends from the termination trench (12) to overlie adjacent regions of the device above the surface. A channel stop region (11) extends laterally from a side wall of the termination trench (12) into the substrate (4).

Abstract: A temperature dependent switching circuit comprises a first transistor with a threshold voltage Vth having a negative temperature coefficient. A diode having a forward voltage drop with a negative temperature coefficient coupled with its anode connected to the drain of the first transistor and its cathode connected to the gate of the first transistor. A first resistor is coupled between a power supply terminal and the drain of the first transistor. A low voltage supply is terminal connected to the source of the first transistor. A second resistor is coupled between the gate of the first transistor and the low voltage supply terminal. A switching transistor has its source connected to the low voltage supply terminal and its gate coupled to the drain of the first transistor. The drain of the first transistor provides a voltage with a negative temperature coefficient equal to the sum of the forward voltage drop across the diode and the threshold voltage of the first transistor.

Abstract: A circuit for generating an oscillating signal comprises an oscillator having a power supply input and first and second outputs, outputting first and second pulse trains respectively of the same frequency but out of phase such that when the first pulse train is high the second pulse train is low and when the second pulse train is high the first pulse train is low. First and second transistors are connected in series with the drain of the first transistor connected to a high voltage input relative to the amplitude of the first and second pulse train pulses. The source of the first transistor is connected to the drain of the second transistor. The source of the second transistor is connected to a low voltage input relative to the amplitude of the first and second pulse train pulses. The gate of the first transistor is connected to the first output of the oscillator and the gate of the second transistor is connected to the second output of the oscillator.

Abstract: A method for implanting ions into a surface of a semiconductor structure covered by a layer of insulating material, for example into a trench wall covered by a layer of oxide. A beam of ions is directed at a glancing angle to the layer of insulating material such that a substantial proportion of ions which are implanted into the semiconductor structure surface are scattered from the beam by the layer of insulating material. It is possible therefore to implant ions into a trench wall without requiring a beam source arranged to deliver a beam at a large angle to the trench wall surface.

Abstract: A current-limit circuit comprising a control transistor coupled to a power transistor in a current mirror configuration. A switch transistor is operatively coupled between the output of the power transistor and the control transistor to selectively activate the control transistor in response to an over current condition detected by a defect transistor. Current drawn through the power transistor in the over current condition is limited by the control transistor which is powered from the gate of the power transistor. The power and detect transistors are integrated on a semi-conductor substrate of a first conductivity type defining first and second surfaces. An array of adjacent transistor body regions of a second conductivity type provided adjacent said first surface with gate electrodes extending between adjacent body regions and insulated therefrom by a gate insulator layer. Transistor source regions of said first conductivity type are provided in said body regions adjacent said gate electrodes.