Abstract: A method for protecting a circuit from a high energy pulse includes placing a PPTC resistive element in series with the circuit and placing an energy pulse clamping semiconductor diode in shunt across the circuit and further includes forming the diode to have: a substrate with carriers of a first type of conductivity in a first, high concentration level (e.g. n++), a first major face and a second major face opposite to the first major face; a layer of semiconductor material having carriers of the first type of conductivity in a second concentration level lower than the first level (e.g. n+), and an outer surface; a region formed at an outer surface having carriers of a second type of conductivity in a third concentration level (e.g. p+); at least one cell having carriers of the second type of conductivity in a fourth concentration level greater than the third concentration level (e.g. p++); and, a cathode electrode and an anode electrode.

Abstract: A two-terminal barrier controlled TVS diode has a depletion region barrier blocking majority carrier flow through the channel region at the vicinity of the cathode region at bias levels below the predetermined clamping voltage applied between the anode electrode and the cathode electrode, and may be arranged such that the anode region provides conductivity modulation by injecting minority carriers into the channel region during conduction of the semiconductor structure. In presently preferred form the majority carriers are electrons and the minority carriers are holes. Fabrication methods are described.

Abstract: A two-terminal barrier controlled TVS diode has a depletion region barrier blocking majority carrier flow through the channel region at the vicinity of the cathode region at bias levels below the predetermined clamping voltage applied between the anode electrode and the cathode electrode, and may be arranged such that the anode region provides conductivity modulation by injecting minority carriers into the channel region during conduction of the semiconductor structure. In presently preferred form the majority carriers are electrons and the minority carriers are holes. Fabrication methods are described.

Abstract: An electrical device includes a package having an array of connections, a thermally conductive, electrically insulative substrate in the package, a plurality of polymeric positive temperature coefficient (PPTC) resistors in the package in thermal contact with the substrate, and, at least one heating element such as a power field effect transistor in thermal contact with the substrate, for indirectly heating the PPTC resistors in response to a control current, thereby to trip the PPTC resistors from a low resistance state to a very high resistance state. A method for controlling a plurality of electrical loads is also disclosed.

Abstract: An electrical device includes a package having an array of connections, a thermally conductive, electrically insulative substrate in the package, a plurality of polymeric positive temperature coefficient (PPTC) resistors in the package in thermal contact with the substrate, and, at least one heating element such as a power field effect transistor in thermal contact with the substrate, for indirectly heating the PPTC resistors in response to a control current, thereby to trip the PPTC resistors from a low resistance state to a very high resistance state. A method for controlling a plurality of electrical loads is also disclosed.

Abstract: The present invention provides simple, low cost power control circuits and methods for high frequency (e.g., RF) applications. According to one embodiment of the present invention, a high frequency circuit comprises a capacitor, a PTC element and a resistor. The PTC element is heated by a high frequency input signal and changes its resistance. The change in the resistance of the PTC element controls the output power of the circuit. In another embodiment of the present invention, the circuit comprises a high frequency circuit and a control circuit. The control circuit provides a DC current to the high frequency circuit to control the resistance of the PTC element, which in turn controls the output power of the high frequency circuit. In this embodiment, two separate paths are used: one for high frequency input signals and one for DC control current.

Abstract: A method and apparatus for providing a more reliable protection device and an improved PIC power integrated switch. Accordingly, the over-temperature status of the switch as well as the overcurrent status of each of a plurality of ports of the switch are detected. If there is over-temperature, ports with the overcurrent status are identified as a potential cause. These ports are then switched off. After a predetermined waiting time period during which the switch temperature is expected to decrease, the over-temperature status of the switch is again checked. If the over-temperature disappears, then the ports with non-overcurrent status remain on. However, if the over-temperature persists, then all of the ports are turned off. The improved PIC switch thus increases the dynamic operation range of the conventional PIC switch, while ensuring normal operations.

Abstract: The present invention provides a two-terminal, transistor-PTC, circuit protection device that has a reduced size and weight and is particularly suitable for use, for example, in portable electronic devices and high density electronic circuits. According to one embodiment of the present invention, a circuit protection device comprises a positive coefficient temperature (PTC) element and a bipolar transistor having base, collector, and emitter terminals. The PTC element is connected between the base and collector terminals of the transistor. The PTC element may be thermally coupled to the transistor and packaged with the transistor as a hybrid device. An electrical load may be connected to the collector terminal of the transistor. According to another embodiment of the present invention, a circuit protection device comprises a PTC element and a Darlington circuit having base, collector and emitter terminals. The PTC element is connected between the base and collector terminals of the Darlington circuit.

Abstract: A circuit protection device for protecting an electrical load includes a three-terminal switch element such as a bipolar, or junction or metal-oxide-semiconductor field effect, transistor and a positive temperature compensation (PTC) resistor. In several embodiments the PTC resistor is in series with the current-carrying electrodes of the transistor. In other embodiments the PTC resistor, or a second PTC resistor, is connected to a control element of the transistor. Both DC and AC load-protection circuits are described.

Abstract: The present invention provides an electronic circuit with adjustable delay time for turning on or off an application device or an electronic load. The electronic circuit according to the present invention comprises a switch element for controlling power supplied to a load; and an activation element, coupled to the switch element, for activating the switch element to control power supplied to the load. The activation element includes a sensor for sensing whether there is a change in condition and for delaying activation by the activation element of the switch element upon sensing a change in condition. In one embodiment of the invention, the sensor includes a positive temperature coefficient (PTC) element; the switch element includes a metal-oxide-semiconductor field effect transistor (MOSFET); and the activation element further includes a capacitor and a switch. A change in condition includes an overload and an increase in the ambient temperature.

Abstract: The present invention provides a simple, low cost power line protection device and method suitable for protecting data bus and power lines such as in the USB (Universal Serial Bus) configurations and other power management circuits. In one embodiment of the invention, an improved protection device, controllable by a control circuit, for protecting a power line is provided. The device includes a switch for switching on and off power supplied on the power line, and a detector for detecting a fault condition, such as an overload condition, on the power line. The detector includes a positive temperature coefficient (PTC) resistor thermally coupled to the switch for causing the fault condition to be reported to the control circuit. In this way, when a fault condition occurs, the control circuit activates the switch to switch off power supplied on the power line.

Abstract: A BIFET vacuum tube replacement structure includes a plurality of devices that replicate the characteristics of a vacuum tube. The vacuum tube replacement structure has the same pin-out as the vacuum tube being replaced and so can be exchanged directly for a vacuum tube in an audio amplifier. The vacuum tube replacement structure is suitable for use in a wide range of audio amplifier applications without modification to the audio amplifiers. Further, there is no noticeable degradation to the human ear in the sound quality when the vacuum tube replacement structure is used in an audio amplifier in place of a vacuum tube. A unitary device that is a combination of a high impedance bipolar like transistor and a unipolar junction field effect transistor, that is referred to as a BIFET, is used in the vacuum tube replacement structure. In one embodiment, the bipolar like transistor is formed in combination with the gate of the unipolar junction field effect transistor.

Abstract: A transistor constructed in accordance with our invention includes an N+ substrate, an N- region formed on the N+ substrate, a P- body region formed on the N- region, and an N+ source region formed on the P- body region. A vertical groove extends through the N+, P- and N- regions, and an insulating layer is formed on the groove walls. A polysilicon gate is formed inside the groove. Of importance, the portion of the insulating layer between the polysilicon and the N+ region and the insulating layer between the polysilicon and the N+ substrate is thicker than the portion of the insulating layer between the polysilicon gate and the P- body region. Because of the enhanced thickness of the portions of the .insulating layer between the gate and N+ substrate, the transistor constructed in accordance with our invention is less susceptible to premature field induced breakdown.

Abstract: The junction field effect transistors (JFETs) of this invention have improved breakdown voltage capability, reduced on-resistance and improved overdrive capability. The JFET on-resistance is decreased by ion-implanting an insulating layer covering a layer that contains the source and gate regions of the unipolar transistor. The charge of the implanted ions is the same as the charge polarity of the gate regions. To improve the overdrive capability of a JFET a region of conductivity opposite to the conductivity of the gate region is formed in the gate region of the transistor. This region of opposite conductivity creates another junction within the gate region i.e., the junction between the region of opposite conductivity and the gate region, and the junction between the gate region and the layer containing the gate region.

Abstract: A transistor includes an N+ substrate, an N- region formed on the N+ substrate, a P- body region formed on the N- region, and an N+ source region formed on the P- body region. A vertical groove extends through the N+, P- and N- regions, and an insulating layer is formed on the groove walls. A polysilicon gate is formed inside the groove. Of importance, the portion of the insulating layer between the polysilicon and the N+ region and the insulating layer between the polysilicon and the N+ substrate is thicker than the portion of the insulating layer between the polysilicon gate and the P- body region. Because of the enhanced thickness of the portions of the insulating layer between the gate and N+ substrate, the transistor constructed in accordance with our invention is less susceptible to premature field induced breakdown.

Abstract: A transistor constructed in accordance with our invention includes an N+ substrate, an N- region formed on the N+ substrate, a P- body region formed on the N- region, and an N+ source region formed on the P- body region. A vertical groove extends through the N+, P- and N- regions, and an insulating layer is formed on the groove walls. A polysilicon gate is formed inside the groove. Of importance, the portion of the insulating layer between the polysilicon and the N+ region and the insulating layer between the polysilicon and the N+ substrate is thicker than the portion of the insulating layer between the polysilicon gate and the P- body region. Because of the enhanced thickness of the portions of the insulating layer between the gate and N+ substrate, the transistor constructed in accordance with our invention is less susceptible to premature field induced breakdown.

Abstract: A semiconductor device, specifically an FET, having a body which includes a matrix of semiconductor material, specifically silicon, having an array of individual rods of conductive material, specifically TaSi.sub.2, disposed therein. The rods form Schottky barriers with the semiconductor material. A gate contact is made to several of the rods at one end, and source and drain contacts are made to the matrix of semicondcutor material. Current flow in the semiconductor material of the matrix between the source and the drain is controlled by applying biasing potential to the gate contact to enlarge the depletion zones around the rods.

Abstract: A trench power MOSFET device is disclosed wherein the method of manufacturing produces a high density MOSFET cell with good breakdown characteristics.

Abstract: A junction field effect transistor (JFET) with a novel gate. The novel gate uses a gate region (19) induced by charged ions (13) located in the gate dielectric layer (12) above the channel region (1). The charged ions (13) that induce the gate region are implanted into the gate dielectric layer (12) and subsequently activated. Both N channel and P channel devices can be produced in this fashion. The invention, unlike conventional JFET's, may be forward biased, and is free of the noise produced by a conventional diffused gate region.

Abstract: A power MOS transistor includes a polycrystalline silicon layer which provides connection to act as a resistor between a first portion of gate metallization disposed above the gate of the device, and a second portion of gate metalization adjacent to the active source/gate region of the device.