Abstract: A method of erecting a carton from a blank, including: engaging the blank with a punch head against which the carton is formed, folding side portions of the blank against the punch head to form sides of the carton; folding outer portions of the side portions of the blank away from the punch head and against an external side of the carton; folding end portions of the blank against the punch head to form end portions of the carton; folding outer portions of the end portions of the blank away from the punch head and against an external end of the carton; and securing corner gussets formed between the side and end portions against sides or ends of the carton.

Abstract: A multi-threaded imperative programming language includes a language construct defining a function call. A circuit implementation for the construct includes a first pipeline, a second pipeline, and a third pipeline. The first hardware pipeline outputs variables to a first queue and outputs parameters for the function to a second queue. The second hardware pipeline obtains the function parameters from the second queue, performs the function, and stores the results of the function in a third queue. The third hardware pipeline retrieves the results generated by the second pipeline from the second queue and retrieves the variables from the first queue. The third hardware pipeline performs hardware operations specified by the source code using the variables and the results of the function. A single instance of the circuit implementation can be utilized to implement calls to the same function made from multiple locations within source code.

Abstract: Various embodiments are described herein for a system and a method for assessing a risk of ventricular arrhythmias for a patient. For example, the method may comprise receiving ECG data obtained from the patient; analyzing the ECG data to detect abnormal QRS peaks; determining the risk of ventricular arrhythmias for the patient based on the detected abnormal QRS peaks; and providing an indication of the risk of ventricular arrhythmias for the patient. The system may be configured to perform this method.

Abstract: A multi-threaded imperative programming language includes a language construct defining a function call. A circuit implementation for the construct includes a first pipeline, a second pipeline, and a third pipeline. The first hardware pipeline outputs variables to a first queue and outputs parameters for the function to a second queue. The second hardware pipeline obtains the function parameters from the second queue, performs the function, and stores the results of the function in a third queue. The third hardware pipeline retrieves the results generated by the second pipeline from the second queue and retrieves the variables from the first queue. The third hardware pipeline performs hardware operations specified by the source code using the variables and the results of the function. A single instance of the circuit implementation can be utilized to implement calls to the same function made from multiple locations within source code.

Abstract: A masked packet checksum is utilized to provide error detection and/or error correction for only discrete portions of a packet, to the exclusion of other portions, thereby avoiding retransmission if transmission errors appear only in portions excluded by the masked packet checksum. A bitmask identifies packet portions whose data is to be protected with error detection and/or error correction schemes, packet portions whose data is to be excluded from such error detection and/or error correction schemes, or combinations thereof. A bitmask can be a per-packet specification, incorporated into one or more fields of individual packets, or a single bitmask can apply equally to multiple packets, which can be delineated in numerous ways, and can be separately transmitted or derived. Bitmasks can be generated at higher layers with lower layer mechanisms deactivated, or can be generated lower layers based upon data passed down.

Abstract: A multi-threaded imperative programming language includes language constructs that map to circuit implementations. The constructs can include a condition statement that enables a thread in a hardware pipeline to wait for a specified condition to occur, identify the start and end of a portion of source code instructions that are to be executed atomically, or indicate that a read-modify-write memory operation is to be performed atomically. Source code that includes one or more constructs mapping to a circuit implementation can be compiled to generate a circuit description. The circuit description can be expressed using hardware description language (HDL), for instance. The circuit description can, in turn, be used to generate a synchronous digital circuit that includes the circuit implementation. For example, HDL might be utilized to generate an FPGA image or bitstream that can be utilized to program an FPGA that includes the circuit implementation associate with the language construct.

Abstract: Program source code defined in a multi-threaded imperative programming language can be compiled into a circuit description for a synchronous digital circuit (“SDC”) that includes pipelines and queues. During compilation, data defining a debugging network for the SDC can be added to the circuit description. The circuit description can then be used to generate the SDC such as, for instance, on an FPGA. A CPU connected to the SDC can utilize the debugging network to query the pipelines for state information such as, for instance, data indicating that an input queue for a pipeline is empty, data indicating the state of an output queue, or data indicating if a wait condition for a pipeline has been satisfied. A profiling tool can execute on the CPU for use in debugging the SDC.

Abstract: A programming language and a compiler are disclosed that optimize the use of look-up tables (LUTs) on a synchronous digital circuit (SDC) such as a field programmable gate array (FPGA) that has been programmed. LUTs are optimized by merging multiple computational operations into the same LUT. A compiler parses source code into an intermediate representation (IR). Each node of the IR that represents an operator (e.g. ‘&’, ‘+’) is mapped to a LUT that implements that operator. The compiler iteratively traverses the IR, merging adjacent LUTs into a LUT that performs both operations and performing input removal optimizations. Additional operators may be merged into a merged LUT until all the LUT's inputs are assigned. Pipeline stages are then generated based on merged LUTs, and an SDC is programmed based on the pipeline and the merged LUT.

Abstract: A masked packet checksum is utilized to provide error detection and/or error correction for only discrete portions of a packet, to the exclusion of other portions, thereby avoiding retransmission if transmission errors appear only in portions excluded by the masked packet checksum. A bitmask identifies packet portions whose data is to be protected with error detection and/or error correction schemes, packet portions whose data is to be excluded from such error detection and/or error correction schemes, or combinations thereof. A bitmask can be a per-packet specification, incorporated into one or more fields of individual packets, or a single bitmask can apply equally to multiple packets, which can be delineated in numerous ways, and can be separately transmitted or derived. Bitmasks can be generated at higher layers with lower layer mechanisms deactivated, or can be generated lower layers based upon data passed down.

Abstract: The invention provides a compound of formula (I), or pharmaceutically acceptable ester, amide, carbamate, solvate or salt thereof, including a salt of such an ester, amide or carbamate, wherein R1 is an optionally substituted phenyl, or an optionally substituted 5- or 6-membered aromatic heterocycle; and R2 is an optionally substituted 5- or 6-membered aromatic heterocycle. Also provided are pharmaceutical compositions comprising a compound of formula (I).

Abstract: A multi-threaded programming language and compiler generates synchronous digital circuits that maintain thread execution order by generating pipelines with code paths that have the same number of stages. The compiler balances related code paths within a pipeline by adding additional stages to a code path that has fewer stages. Programming constructs that, by design, allow thread execution to be re-ordered, may be placed in a reorder block construct that releases threads in the order they entered the programming construct. First-in-first-out (FIFO) queues pass local variables between pipelines. Local variables are popped from FIFOs in the order they were pushed, preserving thread execution order across pipelines.

Abstract: Provided herein are methods of preparing a template nucleic acid for next-generation sequencing. The methods comprise performing primer extension using c7dGTP instead of dGTP, which then allows for the input nucleic acids to be selectively digested by c7dGTP-resistant restriction enzymes, thereby enriching the template nucleic acid prior to next-generation sequencing library preparation.

Abstract: System, method and computer program product of assessing the likelihood of response to cardiac resynchronization therapy (CRT) for a patient. ECG data is obtained from the patient and is analyzed to detect abnormal QRS peaks. A likelihood of the patient responding to CRT is determined based on the number of abnormal QRS peaks detected. An indication of whether the patient is a candidate for CRT can be provided based on the determined likelihood of CRT response. This indication can be used to guide treatment for the patient.

Abstract: Screening systems and methods for inspecting and sterilizing objects include a scanner with an upstream side having an entry shroud and a downstream side having an exit shroud. The scanner houses an inspection volume coupled to a radiation source and a detector array. Ultra-violet light curtains are positioned at the entry shroud and a first conveyor transports objects through the ultra-violet light curtains and into the inspection volume for scanning. A second conveyor transports the objects from the inspection volume after scanning.

Abstract: A server system is provided that includes a plurality of servers, each server including at least one hardware acceleration device and at least one processor communicatively coupled to the hardware acceleration device by an internal data bus and executing a host server instance, the host server instances of the plurality of servers collectively providing a software plane, and the hardware acceleration devices of the plurality of servers collectively providing a hardware acceleration plane that implements a plurality of hardware accelerated services, wherein each hardware acceleration device maintains in memory a data structure that contains load data indicating a load of each of a plurality of target hardware acceleration devices, and wherein a requesting hardware acceleration device routes the request to a target hardware acceleration device that is indicated by the load data in the data structure to have a lower load than other of the target hardware acceleration devices.

Abstract: A masked packet checksum is utilized to provide error detection and/or error correction for only discrete portions of a packet, to the exclusion of other portions, thereby avoiding retransmission if transmission errors appear only in portions excluded by the masked packet checksum. A bitmask identifies packet portions whose data is to be protected with error detection and/or error correction schemes, packet portions whose data is to be excluded from such error detection and/or error correction schemes, or combinations thereof. A bitmask can be a per-packet specification, incorporated into one or more fields of individual packets, or a single bitmask can apply equally to multiple packets, which can be delineated in numerous ways, and can be separately transmitted or derived. Bitmasks can be generated at higher layers with lower layer mechanisms deactivated, or can be generated lower layers based upon data passed down.

Abstract: A language disclosed herein includes a loop construct that maps to a circuit implementation. The circuit implementation may be used to design or program a synchronous digital circuit. The circuit implementation includes a hardware pipeline that implements a body of a loop and a condition associated with the loop. The circuit implementation also includes the hardware first-in-first-out (FIFO) queues that marshal threads (i.e. collections of local variables) into, around, and out of the hardware pipeline. A pipeline policy circuit limits a number of threads allowed within the hardware pipeline to a capacity of the hardware FIFO queues.

Abstract: Active intelligent message filtering can be utilized to provide error resiliency, thereby allowing messages to be received without traditional error detection, and, in turn, avoiding the inefficiency of retransmission of network communications discarded due to network transmission errors detected by such traditional error detection mechanisms. Network transmission errors can result in the receiving application receiving messages that appear to comprise values that differ from the values originally transmitted by the transmitting application. Based on the inaccuracy tolerance applicable to the transmitting and receiving applications, rules can be applied to actively intelligently filter the received messages to replace the received values with the replacement values according to the rules. In such a manner, the receiving application can continue to receive usable data from the transmitting application without any error detection at lower network communication levels.

Abstract: Improving data retrieval by a computer, the data stored exclusively in the computer as a structure comprising a plurality of nodes connected by edges, wherein the edges indicate relationships among the plurality of nodes, and wherein the structure further comprise properties which store information that relate to the plurality of nodes. Metadata is stored as part of the structure, the metadata defining rules for updating the relationships among the plurality of nodes. A command is received to update at least one of the nodes, the edges, or the properties. The at least one of the nodes, the edges, or the properties, are updated according to the rules defined by the metadata.

Abstract: In one embodiment, there is provided a dock for a replaceable fluid container for an engine, the fluid container having: a fluid reservoir; and at least one fluid port having a coupling adapted to couple with a fluid circulation system associated with the engine; the dock having: a fastening mechanism configured to cooperate with the container such that, as the container is inserted into the dock, the fastening mechanism acts first to seat the fluid container in the dock but in an undocked condition and then, as the container is inserted further into the dock, acts to bring the fluid container into an engaged condition in which the fluid container is docked with a docking interface of the dock.