Abstract: A method for identifying erroneous data in at least one memory element, particularly a register, that includes at least one flip-flop that is intended to allow reliable detection of soft errors. To this end, writing of data to the at least one memory element involves at least one write security bit being produced from these data and stored in an associated security memory element, wherein at least one output security bit is computed from the data continuously in the same way as for writing and is compared with the corresponding write security bit.

Abstract: A microcontroller system for safety-critical motor vehicle systems is provided. The microcontroller system includes a plurality of subsystems arranged on a common chip. At least one of the subsystems has more than one channel and is designed to carry out a plurality of operating modes. The subsystems, in a first operating mode, are operated independently of each other and communicate with each other via an on-chip interface. In a second operating mode, at least one of the subsystems is operated by data transmission means and using non-local resources of at least one further subsystem and/or at least one of the subsystems is operating and at least one further subsystem is inactive. A method for operating such a microcontroller system and to the use thereof is also provided.

Abstract: A microcontroller system for safety-critical motor vehicle systems is provided. The microcontroller system includes a plurality of subsystems arranged on a common chip. At least one of the subsystems has more than one channel and is designed to carry out a plurality of operating modes. The subsystems, in a first operating mode, are operated independently of each other and communicate with each other via an on-chip interface. In a second operating mode, at least one of the subsystems is operated by data transmission means and using non-local resources of at least one further subsystem and/or at least one of the subsystems is operating and at least one further subsystem is inactive. A method for operating such a microcontroller system and to the use thereof is also provided.

Abstract: A microprocessor system (50) for controlling or regulating at least partly safety-critical processes, comprising two central processing units (1, 2) integrated in a chip housing, a first and a second bus system, at least one full memory (7) on the first bus system, at least one test data store (51) on the second bus system, which has a reduced store coverage compared to the full memory on the first bus system and in which test data are stored which are connected to data of the memory (7) on the first bus system, and the bus systems comprise comparison and/or driver components which allow the data interchange and/or comparison of data between the two bus systems, and a hardware test data generator (4) is arranged at least on the second bus system, in which case at least part of the full memory on the first bus is additionally backed up using another test data store (5) and test data on the first bus. The invention further relates to the use of the above microprocessor system in motor vehicle controllers.

Abstract: A method for identifying erroneous data in at least one memory element, particularly a register, that includes at least one flip-flop that is intended to allow reliable detection of soft errors. To this end, writing of data to the at least one memory element involves at least one write security bit being produced from these data and stored in an associated security memory element, wherein at least one output security bit is computed from the data continuously in the same way as for writing and is compared with the corresponding write security bit.

Abstract: A redundant two-processor controller having a first processor (1) and a second processor (1) for the synchronous execution of a control program. The controller having at least a first multiplexer (70, 91) for optionally connecting at least a first peripheral unit (72, 95) to be actuated to one of the two processors (1, 2), and at least a first Comparison unit (70, 91) for monitoring the synchronization state of the two processors (1, 2) and for detecting a synchronization error. A restoration control unit (44) is designed to monitor the execution of at least one test program by the two processors (1, 2) after the occurrence of a synchronization error and to evaluate the test results, and which is designed to configure at least the first multiplexer (70, 91).

Abstract: Disclosed is a method of improving the immunity to interference of an integrated circuit (16) having error signals transferred between a microprocessor chip or multiple processor ?C (1) and an additional component (2). For the transfer, a minimum pulse length that is independent of the clock frequency of the microprocessor or the microprocessors is defined, starting from which a signal on an error line having a defined pulse length is interpreted as an error. Also disclosed is an integrated circuit, which is designed so that the above method is implemented. The circuit has a microprocessor chip or multiple processor microcontroller (1) or microprocessor module and an additional component (2) having separately arranged power elements. The circuit also has pulse extending devices and/or signal delaying devices for the output of error pulses (6, 6?) one after the other through at least one error line (3, 4).

Abstract: An integrated circuit arrangement on a common chip or chip support, for safety critical applications, in particular for use in control and regulation units for a motor vehicle braking system, including at least one microprocessor system module, which has at least one core processor, provided with at least one ROM and at least one RAM, at least one power module for controlling external users and at least one monitoring module for monitoring at least parts and/or part systems of the circuit arrangement, the circuit arrangement including at least one temperature sensor for recording a chip temperature.

Abstract: A memory mapping system is connectable to a multi-processing arrangement. The multi-processing arrangement includes a first processing unit and a second processing unit. The memory mapping system includes a main memory to which the second processing unit does not have write access, the main memory including a first memory section and a second memory section. An associated memory is associated with the second memory section. The associated memory includes a memory section to which the second processing unit has write access. A consistency control unit can maintaining consistency between data stored in the associated memory and data stored in the second memory section.

Abstract: A checking method in which serial data protected by check data are transmitted via a serial data bus from a transmitter to a receiver, the receiver then conditions the data and compares them with the transmitted check data in order to recognize transmission errors, wherein the transmitter bases the production of the check data and the receiver bases the conditioning of the data on the same check data formation method, wherein the check data formation/conditioning is performed using error recognition hardware, wherein the region of the receiver contains not only the error recognition hardware but also error recognition software which are used to additionally check the received data, and wherein also an error in the transmitted data and/or check data is caused by a transmitter-end error stimulation. A transmission and reception circuit for carrying out the above method and also the use thereof is also disclosed.

Abstract: A redundant two-processor controller having a first processor (1) and a second processor (1) for the synchronous execution of a control program. The controller having at least a first multiplexer (70, 91) for optionally connecting at least a first peripheral unit (72, 95) to be actuated to one of the two processors (1, 2), and at least a first Comparison unit (70, 91) for monitoring the synchronization state of the two processors (1, 2) and for detecting a synchronization error. A restoration control unit (44) is designed to monitor the execution of at least one test program by the two processors (1, 2) after the occurrence of a synchronization error and to evaluate the test results, and which is designed to configure at least the first multiplexer (70, 91).

Abstract: A semiconductor memory and a data processing system having hardware for carrying out a method for the improved internal monitoring of addressing circuits in semiconductor memories or in a data processing system, in which logic levels addressing lines are tapped off, the actually selected address or subaddress is represented by additional address bit lines, the actually accessed address/subaddress is recovered using the address bit lines, and the actually selected address/subaddress is compared with the applied address/subaddress, obtained from the additional address bit lines, in order to recognize an error in the addressing circuit.

Abstract: The invention relates to a microprocessor system (60) for controlling and/or regulating at least partly security-critical processes, which system comprises two central processing units (1, 2) integrated into a chip housing, a first and a second bus system, at least one complete memory (7) on the first bus system, and check data in one or more check data memories, said data being related to data of the memory in the first bus system. The check data memory is smaller than the complete memory. The bus systems comprise comparative and/or driver components which facilitate data exchange and/or comparison of data between the two bus systems. The one or more check data memories are arranged on the first bus system. On the second bus system, neither a check data memory nor a memory safeguarding data of the memory on the first bus is used. The invention also relates to the use of the inventive microprocessor system in automotive control devices.

Abstract: A memory mapping system is connectable to a multi-processing arrangement. The multi-processing arrangement includes a first processing unit and a second processing unit. The memory mapping system includes a main memory to which the second processing unit does not have write access, the main memory including a first memory section and a second memory section. An associated memory is associated with the second memory section. The associated memory includes a memory section to which the second processing unit has write access. A consistency control unit can maintaining consistency between data stored in the associated memory and data stored in the second memory section.

Abstract: An integrated circuit arrangement on a common chip or chip support, for safety critical applications, in particular for use in control and regulation units for a motor vehicle braking system, including at least one microprocessor system module, which has at least one core processor, provided with at least one ROM and at least one RAM, at least one power module for controlling external users and at least one monitoring module for monitoring at least parts and/or part systems of the circuit arrangement, the circuit arrangement including at least one temperature sensor for recording a chip temperature.

Abstract: A microprocessor system (50) for controlling or regulating at least partly safety-critical processes, comprising two central processing units (1, 2) integrated in a chip housing, a first and a second bus system, at least one full memory (7) on the first bus system, at least one test data store (51) on the second bus system, which has a reduced store coverage compared to the full memory on the first bus system and in which test data are stored which are connected to data of the memory (7) on the first bus system, and the bus systems comprise comparison and/or driver components which allow the data interchange and/or comparison of data between the two bus systems, and a hardware test data generator (4) is arranged at least on the second bus system, in which case at least part of the full memory on the first bus is additionally backed up using another test data store (5) and test data on the first bus. The invention further relates to the use of the above microprocessor system in motor vehicle controllers.

Abstract: A checking method in which serial data protected by check data are transmitted via a serial data bus from a transmitter to a receiver, the receiver then conditions the data and compares them with the transmitted check data in order to recognize transmission errors, wherein the transmitter bases the production of the check data and the receiver bases the conditioning of the data on the same check data formation method, wherein the check data formation/conditioning is performed using error recognition hardware, wherein the region of the receiver contains not only the error recognition hardware but also error recognition software which are used to additionally check the received data, and wherein also an error in the transmitted data and/or check data is caused by a transmitter-end error stimulation. A transmission and reception circuit for carrying out the above method and also the use thereof is also disclosed.

Abstract: The invention relates to a microprocessor system (60) for controlling and/or regulating at least partly security-critical processes, which system comprises two central processing units (1, 2) integrated into a chip housing, a first and a second at least one complete memory (7) on the first bus system, and check data in one or more check data memories, said data being related to data of the memory in the first bus system. The check data memory is smaller than the complete memory. The bus systems comprise comparative and/or driver components which facilitate data exchange and/or comparison of data between the two bus systems. The one or more check data memories are arranged on the first bus system. On the second bus system, neither a check data memory nor a memory safeguarding data of the memory on the first bus is used. The invention also relates to the use of the inventive microprocessor system in automotive control devices.

Abstract: A semiconductor memory and a data processing system having hardware for carrying out a method for the improved internal monitoring of addressing circuits in semiconductor memories or in a data processing system, in which logic levels addressing lines are tapped off, the actually selected address or subaddress is represented by additional address bit lines, the actually accessed address/subaddress is recovered using the address bit lines, and the actually selected address/subaddress is compared with the applied address/subaddress, obtained from the additional address bit lines, in order to recognize an error in the addressing circuit.

Abstract: The invention describes an analyzing device for an embedded system (9), which has at least one CPU (1), at least one CPU bus (2), and at least one memory (3). The device includes a communication module (4) for the input or output of analysis data using a test interface (5), which, in addition to control lines, includes at least one group of data lines. The data words and the address words are transmitted alternately or in other succession by way of the test interface. This achieves the advantage of error detection while using few basic cycles of the CPU.