Abstract: Disclosed is a method of improving the immunity to interference of an integrated circuit (16) having error signals transferred between a microprocessor chip or multiple processor ?C (1) and an additional component (2). For the transfer, a minimum pulse length that is independent of the clock frequency of the microprocessor or the microprocessors is defined, starting from which a signal on an error line having a defined pulse length is interpreted as an error. Also disclosed is an integrated circuit, which is designed so that the above method is implemented. The circuit has a microprocessor chip or multiple processor microcontroller (1) or microprocessor module and an additional component (2) having separately arranged power elements. The circuit also has pulse extending devices and/or signal delaying devices for the output of error pulses (6, 6?) one after the other through at least one error line (3, 4).

Abstract: Disclosed is a system and method for the detection and/or correction of memory access errors in computer systems. Test data (P) is generated in addition to data (D) which is to be secured, using the latter data (D), and is stored inside a memory (4) in such a fashion that a particularly high rate of reliability in error detection and correction can be achieved. To this end, in addition to the data (D) to be secured, the data's addresses are taken into account according to the present system and method when generating the test data (P).

Abstract: The invention discloses an analysis device for an embedded system (9) comprising a CPU (1), a CPU bus (2) and a memory (3). The embedded system has at least one communication module (4) for the input or output of analysis data by way of a test interface (5). The communication module permits the internal memory and the input and output access operations of the embedded system to be monitored and/or logged without using the clock cycles of the CPU (1).

Abstract: The present invention describes a method of storing data words in a RAM module which is especially suited for applications that are critical in terms of safety and includes the following steps: producing a check bit word from at least one data word when writing the at least one data word into the RAM module, storing the check bit word, reading out the check bit word when reading out the at least one data word from the RAM module, regenerating the check bit word from the at least one read-out data word, comparing the read-out check bit word with the regenerated check bit word and generating an error message if they do not correspond. This invention further relates to a corresponding circuit configuration.

Abstract: An electronic digital device for controlling or adjusting processes in a motor vehicle has several components, of which at least one arithmetic unit and a bus connecting the components are redundant. At least one component is not redundant. The electronic device can exhibit a preferably redundant monitoring device which compares the data arising in the redundant systems and outputs an error signal when the data deviate from one another.

Abstract: A circuit for conditioning and digitizing an analog input signal that includes a control circuit taking the form of a delta modulator that has a comparator, a clock-controlled flip-flop, a digital accumulator and a digital-to-analog converter. The comparator compares the analog input signal with an adapted signal. The comparator output is conducted to the flip-flop which produces a binary data stream representative of the difference between the comparator inputs. The digital output signal is generated by the accumulator which if fed with an integration constant that is a function of the output signal of the flip-flop. The digital output signal of the accumulator is converted into a square wave signal, which corresponds to the analog input signal, by way of a digital low-pass filter and a threshold value comparator to which the mean value of the digital output signal is supplied as a threshold value.