Patents by Inventor Advait Mogre

Advait Mogre has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6421400
    Abstract: A digital communications receiver is provided with a PSK demodulator and a soft-decision decoder. The PSK demodulator is configured to accept a receive signal and responsively produce quantized baseband signal components which include a quantized radial component RQ and a quantized angular component &thgr;Q. The soft-decision decoder is coupled to the PSK demodulator to receive the quantized baseband signal components and is configured to convert the quantized signal components into decoded information bits. The soft-decision decoder preferably uses a squared Euclidean distance metric calculation for the decoding process. Using polar coordinate quantization provides an improved performance relative to Cartesian coordinate quantization. A new distance metric for TCM decoding is also provided which requires less implementation complexity than a standards Euclidean distance metric calculation, and which suffers no significant performance loss.
    Type: Grant
    Filed: February 4, 1999
    Date of Patent: July 16, 2002
    Assignee: LSI Logic Corporation
    Inventors: Dojun Rhee, Advait Mogre
  • Patent number: 6157683
    Abstract: A method and system for compensating for code invariancies in a digital communication receiver is performed on demodulated signal data. A pre-Viterbi invariancy compensation is performed on the demodulated signal data to reverse a selected one of a number of possible transformations to create compensated signal data. The compensated signal data is then depunctured. The depunctured data is then decoded. An encoder encodes the decoded data. The encoded data and the depunctured data are then compared to determine equivalence. The pre-Viterbi invariancy compensation is performed to reverse a different one of the number of possible transformations to create the compensated signal data when the encoded data and the depunctured data are determined not to be equivalent. A post-Viterbi invariancy compensation is then performed on the decoded data to produce a set of compensated outputs. Thus, the post-Viterbi invariancy compensation reverses each one of the number of possible transformations on the decoded data.
    Type: Grant
    Filed: February 4, 1998
    Date of Patent: December 5, 2000
    Assignee: LSI Logic Corporatino
    Inventors: Dariush Daribi, Advait Mogre, Daniel Luthi
  • Patent number: 6138265
    Abstract: The present invention performs decoding of trellis coded modulated data using a conventional decoder by splitting up the tasks of estimating the uncoded portion and estimating the coded portion into separate tasks. The task of estimating the coded portion is performed based on a transformation on the input symbols and by taking advantage of the symmetry of the constellation associated with the modulated data when referencing a lookup table. The lookup table may also be designed to be smaller than a straight forward implementation by taking advantage of the same symmetry of the constellation.The alteration of the data is then corrected for, resulting in a smaller constellation (Bi Phase Shift Key for 1 coded bit per symbol systems, Quadrature Phase Shift Key for 2 coded bits per symbol systems) mapping only the coded portion of the data. This allows a conventional Viterbi decoder to estimate the coded portion.
    Type: Grant
    Filed: June 19, 1998
    Date of Patent: October 24, 2000
    Assignee: LSI Logic Corporation
    Inventors: Robert Morelos-Zaragoza, Advait Mogre, Cheng Qian, Rajesh Juluri
  • Patent number: 6134696
    Abstract: The present invention is directed to the encoding and decoding of a digital signal. The encoding process results in a rate-1/n convolutional code derived from a rate-1/2 convolutional code. The process includes: selecting a base convolutional encoding rate of rate-1/l, where l is an integer; selecting an output encoding rate of 1/n, where n is an integer greater than 1; encoding an input digital signal into a convolutional code comprised of signals S(0) through S(l-1), the convolutional code having the rate 1/l convolutional code encoding rate; and providing a rate-1/n convolutional code, which is derived from the rate-1/l convolutional code, the rate-1/n convolutional code having N(i) copies of the rate-1/l signals S(i), where i is from 0 through 1-l and where the sum of N(i) is equal to n.
    Type: Grant
    Filed: May 28, 1998
    Date of Patent: October 17, 2000
    Assignee: LSI Logic Corporation
    Inventors: Robert Morelos-Zaragoza, Advait Mogre