Patents by Inventor Afshin Momtaz

Afshin Momtaz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10476516
    Abstract: A pre-driver circuit includes a differential input circuit to receive a differential-input voltage. A latch circuit can latch voltage levels of output-voltage signals at a differential output port of the pre-driver circuit. A pair of capacitors couple the differential input circuit to the latch circuit. The pre-driver circuit can enable peaking of the output-voltage signals for high-speed operation of the pre-driver circuit and a digital-to-analog converter (DAC)-driver circuit coupled to the pre-driver circuit.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: November 12, 2019
    Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LIMITED
    Inventors: Kun Chuai, Afshin Momtaz, Jun Cao, Seong-Ho Lee, Burak Catli, Anand J. Vasani, Ali Nazemi
  • Publication number: 20190189734
    Abstract: Systems and methods disclosed herein provide a coupled T-coil circuit for differential mode bandwidth extension and common mode rejection. The coupled T-coil circuit includes a first layer including at least a first portion of a first T-coil circuit and a first portion of a second T-coil circuit, and a second layer disposed on top of the first layer and interconnected to the first layer, the second layer including at least a second portion of the first T-coil circuit and a second portion of the second T-coil circuit. The first T-coil circuit includes one or more first coils with a first wind direction. The second T-coil circuit comprises one or more second coils with a second wind direction. The first wind direction can be opposite the second wind direction.
    Type: Application
    Filed: December 20, 2017
    Publication date: June 20, 2019
    Inventors: Guansheng Li, Ullas Singh, Delong Cui, Jun Cao, Afshin Momtaz
  • Patent number: 10033520
    Abstract: A communication system may include a number of communication channels operating in accordance with one or more communication standards. The channels may generate data clocks from one or more master clock signals. The phase of the data clocks may be aligned using phase detectors for determining respective phase relationships and using phase interpolators for adjusting respective clock phases. The communication system may include communication channels that operate at different data clock frequencies. These systems may divide their respective data clocks in order to achieve a common clock frequency for use in their phase alignment. The phase detectors and associated circuitry may be disabled to save power when not in use.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: July 24, 2018
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Adesh Garg, Jun Cao, Namik Kocaman, Kuo-J (Nick) Huang, Delong Cui, Afshin Momtaz
  • Patent number: 10014846
    Abstract: An apparatus for driving a load using a low supply voltage includes a voltage-mode driver and a current source arrangement. The voltage-mode driver provides a desired termination impedance and a first portion of a desired output current to the load. The current source arrangement provides a second portion of the desired output current. The desired output current generates a predetermined voltage swing across the load, while the voltage-mode driver and the current source arrangement are powered by the low supply voltage.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: July 3, 2018
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Afshin Momtaz, Adesh Garg
  • Patent number: 9685969
    Abstract: A time-interleaved digital-to-analog converter (DAC) architecture is provided. The DAC architecture includes a multiplexer/encoder configured to receive a data signal and to generate a plurality of data streams based on the data signal. First and second DAC circuits receive respective first and second data streams of the plurality of data streams and selectively process the respective first and second data streams to generate a respective DAC output signal. The respective DAC output signals of the first and second DAC circuits are coupled together to provide an output signal of the DAC architecture.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: June 20, 2017
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Adesh Garg, Ali Nazemi, Anand Jitendra Vasani, Hyo Gyuem Rhew, Jiawen Zhang, Jun Cao, Meisam Honarvar Nazari, Afshin Momtaz, Tamer Ali
  • Patent number: 9413381
    Abstract: A low-power reconfigurable voltage-mode digital-to-analog converter (DAC) driver circuit includes a first and a second supply voltage and a number of DAC units. Each DAC unit is coupled to a respective bit of a digital input. The DAC units are configured to maintain a constant output impedance. Each DAC unit includes one or more complementary switch pairs that couple first nodes of one or more respective impedances to one of the first or the second supply voltage, based on the respective bit of the digital input. Second nodes of the one or more respective impedances are coupled to an output node.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: August 9, 2016
    Assignee: Broadcom Corporation
    Inventors: Anand Jitendra Vasani, Ali Nazemi, Jun Cao, Afshin Momtaz
  • Publication number: 20160182080
    Abstract: A low-power reconfigurable voltage-mode digital-to-analog converter (DAC) driver circuit includes a first and a second supply voltage and a number of DAC units. Each DAC unit is coupled to a respective bit of a digital input. The DAC units are configured to maintain a constant output impedance. Each DAC unit includes one or more complementary switch pairs that couple first nodes of one or more respective impedances to one of the first or the second supply voltage, based on the respective bit of the digital input. Second nodes of the one or more respective impedances are coupled to an output node.
    Type: Application
    Filed: February 6, 2015
    Publication date: June 23, 2016
    Inventors: Anand Jitendra Vasani, Ali Nazemi, Jun Cao, Afshin Momtaz
  • Patent number: 9325316
    Abstract: A low-power high-swing current-mode logic (CML) driver circuit includes a first differential-pair and a second differential-pair. The first differential-pair includes first transistors, and is coupled to a first voltage supply that supplies a first voltage. The second differential-pair includes second transistors, and a common node of the second differential-pair is coupled to a second voltage supply. The second voltage supply supplies a second voltage that is higher than the first voltage. Control terminals of the first transistors are coupled to control terminals of the second transistors to form input nodes of the driver circuit.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: April 26, 2016
    Assignee: Broadcom Corporation
    Inventors: Amr Amin Hafez Amin Abou-El-Sonoun, Ramy Awad, Mohammed Abdul-Latif, Adesh Garg, Henry Park, Anand Jitendra Vasani, Ullas Singh, Namik Kemal Kocaman, Afshin Momtaz
  • Patent number: 9306621
    Abstract: Methods, systems, and apparatuses are described for reducing the latency in a transceiver. A transceiver includes a high latency communication channel and a low latency communication channel that is configured to be a bypass channel for the high latency communication channel. The low latency communication channel may be utilized when implementing the transceiver is used in low latency applications. By bypassing the high latency communication channel, the high latency that is introduced therein (due to the many stages of de-serialization used to reduce the data rate for digital processing) can be avoided. An increase in data rate is realized when the low latency communication channel is used to pass data. A delay-locked loop (DLL) may be used to phase align the transmitter clock of the transceiver with the receiver clock of the transceiver to compensate for a limited tolerance of phase offset between these clocks.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: April 5, 2016
    Assignee: Broadcom Corporation
    Inventors: Heng Zhang, Mehdi Khanpour, Jun Cao, Chang Liu, Afshin Momtaz
  • Patent number: 9281828
    Abstract: Embodiments for reference-less voltage controlled oscillator (VCO) calibration are provided. Embodiments include a VCO calibration module which uses one or more signals from a frequency detector to automatically select a proper VCO band and bring the VCO clock frequency close enough to the data rate. The VCO calibration module uses a calibration code to calibrate the VCO. In embodiments, the calibration code is determined using a frequency search scheme, which includes a discovery phase to determine the proper VCO band, and a binary search phase and a monitoring phase to select the calibration code that brings the VCO clock frequency closest to the data rate.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: March 8, 2016
    Assignee: Broadcom Corporation
    Inventors: Mahyar Kargar, Siavash Fallahi, Namik Kocaman, Afshin Momtaz
  • Patent number: 9246670
    Abstract: A high-speed clock generator device includes a phase-interpolator (PI) circuit, a smoothing block, and inverter-based low-pass filters. The PI circuit receives a multiple clock signals with different phase angles and generates an output clock signal having a correct phase angle. The smoothing block smooths the clock signals with different phase angles and generates a number of smooth clock signals featuring improved linearity. The inverter-based low-pass filters filter harmonics of the clock signals with different phase angles.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: January 26, 2016
    Assignee: Broadcom Corporation
    Inventors: Mahmoud Reza Ahmadi, Siavash Fallahi, Tamer Ali, Ali Nazemi, Hassan Maarefi, Burak Catli, Afshin Momtaz
  • Patent number: 9231571
    Abstract: A programmable frequency receiver includes a slicer for receiving data at a first frequency, a de-multiplexer for de-multiplexing the data at a second frequency, a programmable clock generator for generating a clock at the first frequency, and first and second resonant clock amplifiers for amplifying clock signals at the first and second frequencies. The resonant clock amplifiers include an inductor having a low Q value, allowing them to amplify clock signals over the programmable frequency range of the receiver. The second resonant clock amplifier includes digitally tunable delay elements to delay and center the amplified clock signal of the second frequency in the data window at the interface between the slicer and the de-multiplexer. The delay elements can be capacitors. A calibration circuit adjusts capacitive elements within a master clock generator to generate a master clock at the first frequency.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: January 5, 2016
    Assignee: Broadcom Corporation
    Inventors: Bharath Raghavan, Jun Cao, Afshin Momtaz
  • Publication number: 20150381150
    Abstract: An apparatus for driving a load using a low supply voltage includes a voltage-mode driver and a current source arrangement. The voltage-mode driver provides a desired termination impedance and a first portion of a desired output current to the load. The current source arrangement provides a second portion of the desired output current. The desired output current generates a predetermined voltage swing across the load, while the voltage-mode driver and the current source arrangement are powered by the low supply voltage.
    Type: Application
    Filed: July 21, 2014
    Publication date: December 31, 2015
    Inventors: Afshin MOMTAZ, Adesh GARG
  • Publication number: 20150304098
    Abstract: A communication system may include a number of communication channels operating in accordance with one or more communication standards. The channels may generate data clocks from one or more master clock signals. The phase of the data clocks may be aligned using phase detectors for determining respective phase relationships and using phase interpolators for adjusting respective clock phases. The communication system may include communication channels that operate at different data clock frequencies. These systems may divide their respective data clocks in order to achieve a common clock frequency for use in their phase alignment. The phase detectors and associated circuitry may be disabled to save power when not in use.
    Type: Application
    Filed: June 30, 2015
    Publication date: October 22, 2015
    Inventors: Adesh Garg, Jun Cao, Namik Kocaman, Kuo-J (Nick) Huang, Delong Cui, Afshin Momtaz
  • Patent number: 9100167
    Abstract: A communication system may include a number of communication channels operating in accordance with one or more communication standards. The channels may generate data clocks from one or more master clock signals. The phase of the data clocks may be aligned using phase detectors for determining respective phase relationships and using phase interpolators for adjusting respective clock phases. The communication system may include communication channels that operate at different data clock frequencies. These systems may divide their respective data clocks in order to achieve a common clock frequency for use in their phase alignment. The phase detectors and associated circuitry may be disabled to save power when not in use.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: August 4, 2015
    Assignee: Broadcom Corporation
    Inventors: Adesh Garg, Jun Cao, Namik Kocaman, Kuo-J Huang, Delong Cui, Afshin Momtaz
  • Publication number: 20150207502
    Abstract: Reference-less repeating circuits provide significant advantages over repeating circuits requiring external frequency references. These repeating circuits eliminate the need for external frequency references provide significant power, layout, and physical isolation advantages. Digitally controlled reference-less repeating circuits have a relatively narrow frequency detection range, but typically consume significantly less power than analog repeating circuits while providing data rate flexibility, particularly at lower data rates. Due to the narrow frequency detection range of digitally controlled reference-less repeating circuits, efficient frequency estimation techniques allow these circuits to quickly lock to an input signal, and provide an accurate repeated output signal.
    Type: Application
    Filed: April 7, 2014
    Publication date: July 23, 2015
    Applicant: BROADCOM CORPORATION
    Inventors: MAGESH VALLIAPPAN, AFSHIN MOMTAZ, NAMIK KOCAMAN, VASUDEVAN PARTHASARATHY
  • Patent number: 9077328
    Abstract: Reference-less repeating circuits provide significant advantages over repeating circuits requiring external frequency references. These repeating circuits eliminate the need for external frequency references provide significant power, layout, and physical isolation advantages. Digitally controlled reference-less repeating circuits have a relatively narrow frequency detection range, but typically consume significantly less power than analog repeating circuits while providing data rate flexibility, particularly at lower data rates. Due to the narrow frequency detection range of digitally controlled reference-less repeating circuits, efficient frequency estimation techniques allow these circuits to quickly lock to an input signal, and provide an accurate repeated output signal.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: July 7, 2015
    Assignee: Broadcom Corporation
    Inventors: Magesh Valliappan, Afshin Momtaz, Namik Kocaman, Vasudevan Parthasarathy
  • Publication number: 20150180649
    Abstract: A high-speed clock generator device includes a phase-interpolator (PI) circuit, a smoothing block, and inverter-based low-pass filters. The PI circuit receives a multiple clock signals with different phase angles and generates an output clock signal having a correct phase angle. The smoothing block smooths the clock signals with different phase angles and generates a number of smooth clock signals featuring improved linearity. The inverter-based low-pass filters filter harmonics of the clock signals with different phase angles.
    Type: Application
    Filed: March 3, 2015
    Publication date: June 25, 2015
    Inventors: Mahmoud Reza AHMADI, Siavash FALLAHI, Tamer ALI, Ali NAZEMI, Hassan MAAREFI, Burak CATLI, Afshin MOMTAZ
  • Patent number: 9024659
    Abstract: A device for passive equalization and slew-rate control of a signal includes a first branch and a second branch. The first branch includes a first driver coupled in series with an equalization capacitor. The second branch includes a second driver coupled in series with a resistor. The second branch may be coupled in parallel to the first branch. The first branch may be configurable to enable either passive equalization or slew-rate control of the signal based on a mode control signal.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: May 5, 2015
    Assignee: Broadcom Corporation
    Inventors: Tamer Ali, Hassan Maarefi, Mahmoud Reza Ahmadi, Afshin Momtaz
  • Patent number: RE45557
    Abstract: A phase lock loop with multiple divider paths is presented herein. The phase lock loop can be used to provide a wide range of frequencies. The phase lock loop can also be used as a portion of a clock multiplier unit or a clock data and recovery unit.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: June 9, 2015
    Assignee: Broadcom Corporation
    Inventors: Mario Caresosa, Namik Kocaman, Afshin Momtaz