Patents by Inventor Afshin Momtaz
Afshin Momtaz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140126613Abstract: Methods, systems, and apparatuses are described for reducing the latency in a transceiver. A transceiver includes a high latency communication channel and a low latency communication channel that is configured to be a bypass channel for the high latency communication channel. The low latency communication channel may be utilized when implementing the transceiver is used in low latency applications. By bypassing the high latency communication channel, the high latency that is introduced therein (due to the many stages of de-serialization used to reduce the data rate for digital processing) can be avoided. An increase in data rate is realized when the low latency communication channel is used to pass data. A delay-locked loop (DLL) may be used to phase align the transmitter clock of the transceiver with the receiver clock of the transceiver to compensate for a limited tolerance of phase offset between these clocks.Type: ApplicationFiled: November 7, 2012Publication date: May 8, 2014Applicant: Broadcom CorporationInventors: Heng Zhang, Mehdi Khanpour, Jun Cao, Chang Liu, Afshin Momtaz
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Publication number: 20140104086Abstract: Methods and apparatuses are described for a DSP receiver with an analog-to-digital converter (ADC) having high speed, low BER performance with low power and area requirements. Speed is increased for multi-path ADC configurations by resolving a conventional bottleneck. ADC performance is improved by integrating calibration and error detection and correction, such as distributed offset calibration and redundant comparators. Power and area requirements are dramatically reduced by using low BER rectification to nearly halve the number of comparators in a conventional high speed, low BER flash ADC.Type: ApplicationFiled: January 30, 2013Publication date: April 17, 2014Applicant: Broadcom CorporationInventors: Bo Zhang, Ali Nazemi, Mahmoud Reza Ahmadi, Afshin Momtaz, Heng Zhang, Hassan Maarefi
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Publication number: 20140079169Abstract: A programmable frequency receiver includes a slicer for receiving data at a first frequency, a de-multiplexer for de-multiplexing the data at a second frequency, a programmable clock generator for generating a clock at the first frequency, and first and second resonant clock amplifiers for amplifying clock signals at the first and second frequencies. The resonant clock amplifiers include an inductor having a low Q value, allowing them to amplify clock signals over the programmable frequency range of the receiver. The second resonant clock amplifier includes digitally tunable delay elements to delay and center the amplified clock signal of the second frequency in the data window at the interface between the slicer and the de-multiplexer. The delay elements can be capacitors. A calibration circuit adjusts capacitive elements within a master clock generator to generate a master clock at the first frequency.Type: ApplicationFiled: November 14, 2013Publication date: March 20, 2014Applicant: BROADCOM CORPORATIONInventors: Bharath RAGHAVAN, Jun CAO, Afshin MOMTAZ
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Patent number: 8618835Abstract: An apparatus is disclosed for converting signals from one digital integrated circuit family to be compatible with another digital integrated circuit family. The apparatus includes a primary interface and a secondary interface to convert a differential output signal from one digital integrated circuit family for use as an input signal by another digital integrated circuit family. The primary and secondary interfaces include gain stages that are configurable to provide rail to rail voltage swings and are characterized as having single pole architectures. The secondary interface may be unterminated such that a substantially equal load is presented to both components of the differential output signal.Type: GrantFiled: September 23, 2011Date of Patent: December 31, 2013Assignee: Broadcom CorporationInventors: Burak Catli, Ali Nazemi, Mahmoud Reza Ahmadi, Ullas Singh, Jun Cao, Afshin Momtaz
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Patent number: 8618964Abstract: According to one general aspect, a distributed threshold adjuster (DTA) may be interspersed between stages of a multistage amplifier to adjust the DC voltage of an input signal. The DTA may include an input signal terminal configured to receive the input signal. The DTA may also include a plurality of current sources configured to produce an adjustment current signal whose amperage is configured to be increased or decreased by fixed steps in order to adjust the DC voltage of the input signal. The DTA may include a control unit configured to selectively turn on or off the individual current sources of the plurality of current sources to select the amperage of the adjustment current signal. The DTA may further include an output terminal configured to produce an output signal, comprising a combination of the input signal and the adjustment current signal, to a stage of a multistage amplifier.Type: GrantFiled: August 11, 2011Date of Patent: December 31, 2013Assignee: Broadcom CorporationInventors: Afshin Momtaz, Namik Kocaman, Bharath Raghavan
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Patent number: 8611379Abstract: A programmable frequency receiver includes a slicer for receiving data at a first frequency, a de-multiplexer for de-multiplexing the data at a second frequency, a programmable clock generator for generating a clock at the first frequency, and first and second resonant clock amplifiers for amplifying clock signals at the first and second frequencies. The resonant clock amplifiers include an inductor having a low Q value, allowing them to amplify clock signals over the programmable frequency range of the receiver. The second resonant clock amplifier includes digitally tunable delay elements to delay and center the amplified clock signal of the second frequency in the data window at the interface between the slicer and the de-multiplexer. The delay elements can be capacitors. A calibration circuit adjusts capacitive elements within a master clock generator to generate a master clock at the first frequency.Type: GrantFiled: April 26, 2011Date of Patent: December 17, 2013Assignee: Broadcom CorporationInventors: Bharath Raghavan, Jun Cao, Afshin Momtaz
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Publication number: 20130285752Abstract: Embodiments provide a reference-less frequency detector that overcomes the “dead zone” problem of conventional circuits. In particular, the frequency detector is able to accurately resolve the polarity of the frequency difference between the VCO clock signal and the data signal, irrespective of the magnitude of the frequency difference and the presence of VCO clock jitter and/or ISI on the data signal.Type: ApplicationFiled: June 28, 2013Publication date: October 31, 2013Inventors: Mahyar KARGAR, Siavash Fallahi, Namik Kocaman, Mehdi Khanpour, Afshin Momtaz
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Publication number: 20130243072Abstract: According to an example embodiment, a communications receiver may include a variable gain amplifier (VGA) configured to amplify received signals, a VGA controller configured to control the VGA, a plurality of analog to digital converter (ADC) circuits coupled to an output of the VGA, wherein the plurality of ADC circuits are operational when the communications receiver is configured to process signals of a first communications protocol, and wherein only a subset of the ADC circuits are operational when the communications receiver is configured to process signals of a second communications protocol.Type: ApplicationFiled: April 26, 2013Publication date: September 19, 2013Applicant: Broadcom CorporationInventors: Vivek Telang, Hong Chen, Vasudevan Parthasarathy, Jun Cao, Afshin Momtaz, Ali Ghiasi, Chung-Jue Chen
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Publication number: 20130229232Abstract: There is presented a high bandwidth circuit for high-speed transceivers. The circuit may comprise an amplifier combining capacitor splitting, inductance tree structures, and various bandwidth extension techniques such as shunt peaking, series peaking, and T-coil peaking to support data rates of 45 Gbs/s and above while reducing data jitter. The inductance elements of the inductance tree structures may also comprise high impedance transmission lines, simplifying implementation. Additionally, the readily identifiable metal structures of inductors and t-coils, the equal partitioning of the load capacitors, and the symmetrical inductance tree structures may simplify transceiver implementation for, but not limited to, a clock data recovery circuit.Type: ApplicationFiled: April 22, 2013Publication date: September 5, 2013Applicant: Broadcom CorporationInventors: Delong Cui, Afshin Momtaz, Jun Cao
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Patent number: 8502609Abstract: Embodiments provide a reference-less frequency detector that overcomes the “dead zone” problem of conventional circuits. In particular, the frequency detector is able to accurately resolve the polarity of the frequency difference between the VCO clock signal and the data signal, irrespective of the magnitude of the frequency difference and the presence of VCO clock jitter and/or ISI on the data signal.Type: GrantFiled: June 10, 2011Date of Patent: August 6, 2013Assignee: Broadcom CorporationInventors: Mahyar Kargar, Siavash Fallahi, Namik Kocaman, Mehdi Khanpour, Afshin Momtaz
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Patent number: 8483267Abstract: An equalizer that compensates for non-linear effects resulting from a transmitter, a receiver, and/or a communication channel in a communication system. A non-linear decision feedback equalizer compensates for the non-linear effects impressed onto a received symbol by selecting between equalization coefficients based upon a previous received symbol. The received symbol may be represented in form of logic signals based on the binary number system. When the previous received symbol is a binary zero, the non-linear decision feedback equalizer selects an equalization coefficient corresponding to binary zero to compensate for the non-linear effects impressed onto the received symbol. When the previous received symbol is a binary one, the non-linear decision feedback equalizer selects an equalization coefficient corresponding to binary one to compensate for the non-linear effects impressed onto the received symbol.Type: GrantFiled: June 3, 2011Date of Patent: July 9, 2013Assignee: Broadcom CorporationInventor: Afshin Momtaz
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Patent number: 8457190Abstract: Embodiments of a summer block for a Decision Feedback Equalizer are provided herein. The summer block is configured to offset a combination of a Feed Forward Equalized (FFE) data signal and a Feedback Equalized (FBE) data signal by a dc amount: The dc amount is based on at least a weight of a tap previously implemented with an FBE of the DFE. The summer block can be further configured to offset the combination of the FFE data signal and the FBE data signal based on a dc offset value necessary to compensate for asymmetries in the data eye of data received by the FFE over a channel and a dc offset value necessary to compensate for mismatches present in the circuits of the DFE.Type: GrantFiled: September 9, 2010Date of Patent: June 4, 2013Assignee: Broadcom CorporationInventors: Bharath Raghavan, Afshin Momtaz, Jun Cao
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Patent number: 8451058Abstract: There is presented a high bandwidth circuit for high-speed transceivers. The circuit may comprise an amplifier combining capacitor splitting, inductance tree structures, and various bandwidth extension techniques such as shunt peaking, series peaking, and T-coil peaking to support data rates of 45 Gbs/s and above while reducing data jitter. The inductance elements of the inductance tree structures may also comprise high impedance transmission lines, simplifying implementation. Additionally, the readily identifiable metal structures of inductors and t-coils, the equal partitioning of the load capacitors, and the symmetrical inductance tree structures may simplify transceiver implementation for, but not limited to, a clock data recovery circuit.Type: GrantFiled: June 22, 2011Date of Patent: May 28, 2013Assignee: Broadcom CorporationInventors: Delong Cui, Afshin Momtaz, Jun Cao
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Patent number: 8442159Abstract: According to an example embodiment, a communications receiver may include a variable gain amplifier (VGA) configured to amplify received signals, a VGA controller configured to control the VGA, a plurality of analog to digital converter (ADC) circuits coupled to an output of the VGA, wherein the plurality of ADC circuits are operational when the communications receiver is configured to process signals of a first communications protocol, and wherein only a subset of the ADC circuits are operational when the communications receiver is configured to process signals of a second communications protocol.Type: GrantFiled: September 16, 2010Date of Patent: May 14, 2013Assignee: Broadcom CorporationInventors: Vivek Telang, Hong Chen, Vasudevan Parthasarathy, Jun Cao, Afshin Momtaz, Ali Ghiasi, Chung-Jue Chen
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Publication number: 20130076394Abstract: An apparatus is disclosed for converting signals from one digital integrated circuit family to be compatible with another digital integrated circuit family. The apparatus includes a primary interface and a secondary interface to convert a differential output signal from one digital integrated circuit family for use as an input signal by another digital integrated circuit family. The primary and secondary interfaces include gain stages that are configurable to provide rail to rail voltage swings and are characterized as having single pole architectures. The secondary interface may be unterminated such that a substantially equal load is presented to both components of the differential output signal.Type: ApplicationFiled: September 23, 2011Publication date: March 28, 2013Applicant: Broadcom CorporationInventors: Burak Catli, Ali Nazemi, Mahmoud Reza Ahmadi, Ullas Singh, Jun Cao, Afshin Momtaz
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Patent number: 8369453Abstract: An apparatus and method is disclosed to compensate for one or more offsets in a communications signal. A communications receiver may carry out an offset adjustment algorithm to compensate for the one or more offsets. An initial search procedure determines one or more signal metric maps for one or more selected offset adjustment corrections from the one or more offset adjustment corrections. The offset adjustment algorithm determines one or more optimal points for one or more selected offset adjustment correction based upon the one or more signal maps. The adaptive offset algorithm adjusts each of the one or more selected offset adjustment corrections to their respective optimal points and/or each of one or more non-selected offset adjustment corrections to a corresponding one of a plurality of possible offset corrections to provide one or more adjusted offset adjustment corrections. A tracking mode procedure optimizes the one or more adjusted offset adjustment corrections.Type: GrantFiled: December 3, 2008Date of Patent: February 5, 2013Assignee: Broadcom CorporationInventors: Namik Kemal Kocaman, Afshin Momtaz, Velu Chellam Pillai, Vivek Telang, Sundararajan Chidambara, Magesh Valliappan
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Publication number: 20120326788Abstract: There is presented a high bandwidth circuit for high-speed transceivers. The circuit may comprise an amplifier combining capacitor splitting, inductance tree structures, and various bandwidth extension techniques such as shunt peaking, series peaking, and T-coil peaking to support data rates of 45 Gbs/s and above while reducing data jitter. The inductance elements of the inductance tree structures may also comprise high impedance transmission lines, simplifying implementation. Additionally, the readily identifiable metal structures of inductors and t-coils, the equal partitioning of the load capacitors, and the symmetrical inductance tree structures may simplify transceiver implementation for, but not limited to, a clock data recovery circuit.Type: ApplicationFiled: June 22, 2011Publication date: December 27, 2012Applicant: BROADCOM CORPORATIONInventors: Delong Cui, Afshin Momtaz, Jun Cao
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Publication number: 20120328063Abstract: Provided is a low latency high bandwidth clock and data recovery (CDR) system. For example, there is a low latency high bandwidth CDR system including a demultiplexer configured to convert a high frequency input datastream to a low frequency output datastream according to a first latency and a phase error processor at least partially embedded into the demultiplexer and configured to determine a datastream phase error of the high frequency input datastream according to a second latency. The embedded phase error processor allows a portion of a total latency of the CDR system due to the demultiplexer and the phase error processor to be less than a sum of the first and second latencies.Type: ApplicationFiled: June 24, 2011Publication date: December 27, 2012Applicant: BROADCOM CORPORATIONInventors: Anand Jitendra Vasani, Jun Cao, Afshin Momtaz
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Publication number: 20120313714Abstract: Embodiments for reference-less voltage controlled oscillator (VCO) calibration are provided. Embodiments include a VCO calibration module which uses one or more signals from a frequency detector to automatically select a proper VCO band and bring the VCO clock frequency close enough to the data rate. The VCO calibration module uses a calibration code to calibrate the VCO. In embodiments, the calibration code is determined using a frequency search scheme, which includes a discovery phase to determine the proper VCO band, and a binary search phase and a monitoring phase to select the calibration code that brings the VCO clock frequency closest to the data rate.Type: ApplicationFiled: June 10, 2011Publication date: December 13, 2012Applicant: Broadcom CorporationInventors: Mahyar Kargar, Siavash Fallahi, Namik Kocaman, Afshin Momtaz
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Publication number: 20120313715Abstract: Embodiments provide a reference-less frequency detector that overcomes the “dead zone” problem of conventional circuits. In particular, the frequency detector is able to accurately resolve the polarity of the frequency difference between the VCO clock signal and the data signal, irrespective of the magnitude of the frequency difference and the presence of VCO clock jitter and/or ISI on the data signal.Type: ApplicationFiled: June 10, 2011Publication date: December 13, 2012Applicant: Broadcom CorporationInventors: Mahyar Kargar, Siavash Fallahi, Namik Kocaman, Mehdi Khanpour, Afshin Momtaz