Abstract: Methods and devices for receiving a data signal transmitted via load modulation, by detecting current supplied in an amplifier feeding the antenna of the device which transmits the carrier signal.

Abstract: A mixed-mode signal detection apparatus suitable for ISO/IEC 14443 Type A and Type B RFID proximity card applications. The apparatus combines switched capacitor sampling and digital post processing to recover information from Amplitude Shift Keying (ASK) modulated signals. A phase detector triggers a pulse generator, which is used to signal sample and hold units that store the peak value of each carrier signal cycle. The samples are used to form a discrete version of the modulation signal and are post-processed digitally to recover encoded signal information.

Abstract: A decision feedback equalizer, transceiver, and method are provided, the equalizer having at least one comparator, the at least one comparator comprising a first stage, comprising a main branch having two track switches with a resistive load, an offset cancellation branch, a plurality of tap branches with transistor sizes smaller than the main branch, in which previous decisions of the equalizer are mixed with the tap weights using current-mode switching, and a cross coupled latch branch; and a second stage, comprising a comparator module for making decisions based on the outputs of the first stage and a clock input, and a plurality of flip-flops for storing the output of the comparator module.

Abstract: A mixed-mode signal detection apparatus suitable for ISO/IEC 14443 Type A and Type B RFID proximity card applications. The apparatus combines switched capacitor sampling and digital post processing to recover information from Amplitude Shift Keying (ASK) modulated signals. A phase detector triggers a pulse generator, which is used to signal sample and hold units that store the peak value of each carrier signal cycle. The samples are used to form a discrete version of the modulation signal and are post-processed digitally to recover encoded signal information.

Abstract: An analog digital converter with switched-capacitor reset architecture. The analog to digital converter (ADC) includes a plurality of pipelined stages, each stage including an analog to digital converter comprising a pair of comparators outputting signals to a multiplying digital to analog converter (MDAC). The MDAC includes an opamp and a reset circuit connected to inputs of the opamp, the reset circuit including first and second capacitors and switching circuitry for precharging each of the first and second capacitors to a difference between the input and output common-mode voltages of the opamp, and during a reset phase of the MDAC, connecting the first capacitor between a positive input and a negative output of the opamp and connecting the second capacitor between a negative input and a positive output of the opamp to reset the opamp.

Abstract: An analog digital converter with switched-capacitor reset architecture. The analog to digital converter (ADC) includes a plurality of pipelined stages, each stage including an analog to digital converter comprising a pair of comparators outputting signals to a multiplying digital to analog converter (MDAC). The MDAC includes an opamp and a reset circuit connected to inputs of the opamp, the reset circuit including first and second capacitors and switching circuitry for precharging each of the first and second capacitors to a difference between the input and output common-mode voltages of the opamp, and during a reset phase of the MDAC, connecting the first capacitor between a positive input and a negative output of the opamp and connecting the second capacitor between a negative input and a positive output of the opamp to reset the opamp.