Patents by Inventor Ah-Reum Kim

Ah-Reum Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210035504
    Abstract: A display device includes a display panel including a plurality of pixel rows, and a panel driver configured to drive the display panel. The panel driver includes a scan on time decider configured to receive line image data for each of the plurality of pixel rows, and to determine a scan on time change amount for each of the plurality of pixel rows based on the line image data, and a scan control block configured to adjust a scan pulse applied to each of the plurality of pixel rows according to the scan on time change amount.
    Type: Application
    Filed: March 26, 2020
    Publication date: February 4, 2021
    Inventors: Donggyu LEE, Ah Reum KIM, Wontae KIM, SeokYoung YOON
  • Publication number: 20200192997
    Abstract: A semiconductor circuit and a layout system of the semiconductor circuit, the semiconductor circuit including a latch; a feedback inverter that receives an output signal of the latch via a first node and provides a feedback signal to the latch responsive to the output signal of the latch; and an output driver which receives the output signal of the latch via the first node and provides an output signal externally of the semiconductor circuit. The output driver includes an even number of inverters, and the latch, the feedback inverter, and the output driver share a single active region formed without isolation.
    Type: Application
    Filed: August 23, 2019
    Publication date: June 18, 2020
    Inventors: Ah Reum KIM, Min Su KIM, Young O LEE
  • Patent number: 10651828
    Abstract: A flip-flop generates a first feedback signal using a signal generated inside the flip-flop. The flip-flop includes a first stage circuit, a second stage circuit and a third stage circuit. The first stage circuit receives a first data signal and a clock signal and generates a first internal signal through a first node. The second stage circuit receives the first internal signal, the clock signal, and the first feedback signal and generates a second internal signal through a second node. The third stage circuit generates a second data signal by latching the second internal signal when the clock signal is at a first level, using the second internal signal and the clock signal. The second stage circuit cuts off at least one first current path between the second node and a power supply, based on the first feedback signal, when the clock signal is at a second level.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: May 12, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Chul Hwang, Ah-Reum Kim, Min-Su Kim
  • Patent number: 10566977
    Abstract: Provided are semiconductor circuits. A semiconductor circuit includes: a first circuit configured to propagate a value of a first node to a second node based on a voltage level of a clock signal; a second circuit configured to propagate a value of the second node to a third node based on the voltage level of the clock signal; and a third circuit configured to determine a value of the third node based on a voltage level of the second node and the voltage level of the clock signal, wherein the first circuit comprises a first transistor gated to a voltage level of the first node, a second transistor connected in series with the first transistor and gated to the voltage level of the third node, and a third transistor connected in parallel with the first and second transistors and gated to a voltage level of the clock signal to provide the value of the first node to the second node.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: February 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ah-Reum Kim, Hyun Lee, Min-su Kim
  • Publication number: 20190393205
    Abstract: An integrated circuit includes a semiconductor substrate, first through third power rails, first through third selection gate lines, and a row connection wiring. The first through third power rails on the semiconductor substrate extend in a first direction and arranged sequentially in a second direction perpendicular to the first direction. The first through third selection gate lines on the semiconductor substrate extend in the second direction over a first region between the first power rail and the second power rail and a second region between the second power rail and the third power rail, and are arranged sequentially in the first direction. The row connection wiring on the semiconductor substrate extends in the first direction to connect the first selection gate line and the third selection gate line.
    Type: Application
    Filed: January 17, 2019
    Publication date: December 26, 2019
    Inventors: Dae-Seong LEE, Ah-Reum KIM, Min-Su KIM, Jong-Kyu RYU
  • Patent number: 10404240
    Abstract: Provided is a semiconductor device including low power retention flip-flop. The semiconductor device includes a first line to which a global power supply voltage is applied, a second line to which a local power supply voltage is applied, the second line being separated from the first line, a first operating circuit connected to the second line to use the local power supply voltage, a first power gating circuit determining whether the local power supply voltage is applied to the first operating circuit and a first retention flip-flop connected to the first line and the second line, wherein the first retention flip-flop comprises a first circuit including a master latch, a second circuit including a slave latch, and a first tri-state inverter connected between the master latch and the slave latch.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: September 3, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Woo Kim, Min Su Kim, Ah Reum Kim, Chung Hee Kim
  • Publication number: 20190173472
    Abstract: Provided are semiconductor circuits. A semiconductor circuit includes: a first circuit configured to propagate a value of a first node to a second node based on a voltage level of a clock signal; a second circuit configured to propagate a value of the second node to a third node based on the voltage level of the clock signal; and a third circuit configured to determine a value of the third node based on a voltage level of the second node and the voltage level of the clock signal, wherein the first circuit comprises a first transistor gated to a voltage level of the first node, a second transistor connected in series with the first transistor and gated to the voltage level of the third node, and a third transistor connected in parallel with the first and second transistors and gated to a voltage level of the clock signal to provide the value of the first node to the second node.
    Type: Application
    Filed: January 28, 2019
    Publication date: June 6, 2019
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ah-Reum KIM, Hyun LEE, Min-su KIM
  • Publication number: 20190135961
    Abstract: Provided is a hybrid catalyst composition including a first transition metal compound represented by Formula 1 and a second transition metal compound represented by Formula 2, the compounds being different from each other in the Formulae. The hybrid catalyst composition including the first and second transition metal compounds may exhibit high catalytic activity and may prepare a polyolefin having processability and mechanical properties.
    Type: Application
    Filed: March 22, 2016
    Publication date: May 9, 2019
    Inventors: Ui Gab Joung, Dong Wook Jeong, Ah Reum Kim, Seung Il Choi
  • Patent number: 10281595
    Abstract: A method and an apparatus for distinguishing radionuclides are disclosed. The method comprises the steps of: receiving energy generated in one or more radioactive elements; applying energy as a weight for each channel to spectrum of the received energy; and distinguishing the one or more radioactive elements on the basis of the spectrum of the spectrum to which the weight is applied. A radioactive element having an energy value corresponding to a peak value of the spectrum of the energy to which the weight is applied, as an energy value of a Compton edge, is distinguished as the one or more radioactive elements. According to the present invention, it is possible to more accurately monitor radiation even while using a plastic scintillator, and further to improve energy resolution of a plastic scintillator.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: May 7, 2019
    Assignee: KOREA INSTITUTE OF NUCLEAR SAFETY
    Inventors: Hong Suk Kim, Chang-Su Park, Chang-il Choi, Chul Hee Min, Wook-Geun Shin, Hyun-Cheol Lee, Jeong Wan Kwon, Hyungjoon Yu, Ah Reum Kim, Hyeon-Jun Choi, Hyunseok Lee
  • Patent number: 10251824
    Abstract: The present disclosure relates to a method for inducing pluripotent stem cells by inducing reprogramming and/or dedifferentiation of differentiated adult cells using shikimic acid, a plant extract or plant stem cells containing shikimic acid and an extract of dedifferentiated stem cells (callus), pluripotent stem cells prepared by the method and a composition containing the pluripotent stem cells. In accordance with the present disclosure, ethical concerns implicated with the use of eggs to prepare pluripotent stem cells such as embryonic stem cell can be resolved. And, because the plant stem cell extract unharmful to human is used, pluripotent stem cells with proven safety can be prepared and they may be used to develop immunocompatible cell therapy agents suited for individuals. In addition, by pluripotent stem cells from individuals having diseases, the present disclosure will be very useful in studying the cause of diseases and devolving therapeutic strategy.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: April 9, 2019
    Assignees: AMOREPACIFIC CORPORATION, SNU R&DB FOUNDATION
    Inventors: Ah Reum Kim, Su Na Kim, Won Seok Park, Yoo Wook Kwon, Young Bae Park, Hyo Soo Kim, Jae Seung Paek
  • Patent number: 10230373
    Abstract: Provided are semiconductor circuits. A semiconductor circuit includes: a first circuit configured to propagate a value of a first node to a second node based on a voltage level of a clock signal; a second circuit configured to propagate a value of the second node to a third node based on the voltage level of the clock signal; and a third circuit configured to determine a value of the third node based on a voltage level of the second node and the voltage level of the clock signal, wherein the first circuit comprises a first transistor gated to a voltage level of the first node, a second transistor connected in series with the first transistor and gated to the voltage level of the third node, and a third transistor connected in parallel with the first and second transistors and gated to a voltage level of the clock signal to provide the value of the first node to the second node.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: March 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ah-Reum Kim, Hyun Lee, Min-Su Kim
  • Publication number: 20190023816
    Abstract: The invention relates to: a hybrid supported metallocene catalyst includes at least one first metallocene compound among the compounds represented by chemical formula 1, at least one second metallocene compound among the compounds represented by chemical formula 2 and a cocatalyst compound; a method for preparing an ethylene-?-olefin copolymer, comprising polymerizing olefin monomers in the presence thereof; and an ethylene-?-olefin copolymer having improved melt strength.
    Type: Application
    Filed: March 29, 2016
    Publication date: January 24, 2019
    Applicant: HANWHA CHEMICAL CORPORATION
    Inventors: Ah Ra Cho, Ah Reum Kim, Lan Hua Piao, Jun Ho Seo, Song Hee Yang, So Jung Lee, Yu Jeong Lim, Dong Wook Jeong, Seung Il Choi
  • Patent number: 10160775
    Abstract: The present invention relates to a novel group 4 transition metal compound, a method for preparing the compound, a catalyst composition containing the compound, and a method for preparing a polyolefin, comprising a step for forming a polymerization reaction of olefin monomers in the presence of the catalyst composition. The group 4 transition metal compound of the present invention exhibits an excellent catalytic activity and has excellent thermal stability in a polyolefin synthesis reaction, and thus can be used even in a polyolefin synthesis reaction at a high temperature. In addition, the compound of the present invention can be advantageously used in the synthesis process of grade-controlled polyolefin since the weight average molecular weight of the synthesized polyolefin and the octane content in the polymer can be adjusted by varying the kinds of center metal and ligand.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: December 25, 2018
    Assignee: HANWHA CHEMICAL CORPORATION
    Inventors: Ui Gab Joung, Dong Ok Kim, Dong Wook Kim, Ah Reum Kim, Hye Ran Park, Kil Sagong, Sung Hae Jun, Chun Sun Lee, Eun Yeong Hwang
  • Publication number: 20180284296
    Abstract: A method and an apparatus for distinguishing radionuclides are disclosed. The method comprises the steps of: receiving energy generated in one or more radioactive elements; applying energy as a weight for each channel to spectrum of the received energy; and distinguishing the one or more radioactive elements on the basis of the spectrum of the spectrum to which the weight is applied. A radioactive element having an energy value corresponding to a peak value of the spectrum of the energy to which the weight is applied, as an energy value of a Compton edge, is distinguished as the one or more radioactive elements. According to the present invention, it is possible to more accurately monitor radiation even while using a plastic scintillator, and further to improve energy resolution of a plastic scintillator.
    Type: Application
    Filed: May 11, 2015
    Publication date: October 4, 2018
    Inventors: Hong Suk KIM, Chang-Su PARK, Chang-il CHOI, Chul Hee MIN, Wook-Geun SHIN, Hyun-Cheol LEE, Jeong Wan Kwon, Hyungjoon Yu, Ah Reum Kim, Hyeon-Jun Choi, Hyunseok Lee
  • Patent number: 9965996
    Abstract: A timing controller includes an image determining part configured to determine whether an input image is a static image based on input image data, a signal controller configured to shift a timing of a first data enable signal to generate a second data enable signal when the input image is the static image, and a signal generator configured to generate control signals based on the second data enable signal.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: May 8, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Dong-Gyu Lee, Geun Jeong Park, Ah-Reum Kim
  • Publication number: 20180123569
    Abstract: A flip-flop generates a first feedback signal using a signal generated inside the flip-flop. The flip-flop includes a first stage circuit, a second stage circuit and a third stage circuit. The first stage circuit receives a first data signal and a clock signal and generates a first internal signal through a first node. The second stage circuit receives the first internal signal, the clock signal, and the first feedback signal and generates a second internal signal through a second node. The third stage circuit generates a second data signal by latching the second internal signal when the clock signal is at a first level, using the second internal signal and the clock signal. The second stage circuit cuts off at least one first current path between the second node and a power supply, based on the first feedback signal, when the clock signal is at a second level.
    Type: Application
    Filed: June 15, 2017
    Publication date: May 3, 2018
    Inventors: HYUN-CHUL HWANG, AH-REUM KIM, MIN-SU KIM
  • Patent number: 9876500
    Abstract: A semiconductor circuit includes a first circuit, a second circuit, a third circuit, and a fourth circuit. The first circuit determines a value of a first node based on a voltage level of a clock signal, and a voltage level of an enable signal or a voltage level of a scan enable signal. The second circuit determines a value of a second node based on the voltage levels of the first node and the clock signal. The third circuit determines a value of a third node based on a voltage level of the second node. The fourth circuit determines a value of a fourth node based on the voltage levels of the second node and the clock signal. The third circuit includes a first transistor and a second transistor connected in series with each other and gated to the voltage level of the second node to determine the value of the third node. The fourth circuit includes a third transistor that is gated to the voltage level of the clock signal to electrically connect the third node and the fourth node.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: January 23, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ah Reum Kim, Min Su Kim, Chung Hee Kim, Hyun Chul Hwang
  • Publication number: 20170317676
    Abstract: A semiconductor circuit includes a first circuit, a second circuit, a third circuit, and a fourth circuit. The first circuit determines a value of a first node based on a voltage level of a clock signal, and a voltage level of an enable signal or a voltage level of a scan enable signal. The second circuit determines a value of a second node based on the voltage levels of the first node and the clock signal. The third circuit determines a value of a third node based on a voltage level of the second node. The fourth circuit determines a value of a fourth node based on the voltage levels of the second node and the clock signal. The third circuit includes a first transistor and a second transistor connected in series with each other and gated to the voltage level of the second node to determine the value of the third node. The fourth circuit includes a third transistor that is gated to the voltage level of the clock signal to electrically connect the third node and the fourth node.
    Type: Application
    Filed: April 27, 2017
    Publication date: November 2, 2017
    Inventors: AH REUM KIM, MIN SU KIM, CHUNG HEE KIM, HYUN CHUL HWANG
  • Publication number: 20170233415
    Abstract: The present invention relates to a novel group 4 transition metal compound, a method for preparing the compound, a catalyst composition containing the compound, and a method for preparing a polyolefin, comprising a step for forming a polymerization reaction of olefin monomers in the presence of the catalyst composition. The group 4 transition metal compound of the present invention exhibits an excellent catalytic activity and has excellent thermal stability in a polyolefin synthesis reaction, and thus can be used even in a polyolefin synthesis reaction at a high temperature. In addition, the compound of the present invention can be advantageously used in the synthesis process of grade-controlled polyolefin since the weight average molecular weight of the synthesized polyolefin and the octane content in the polymer can be adjusted by varying the kinds of center metal and ligand.
    Type: Application
    Filed: August 28, 2015
    Publication date: August 17, 2017
    Inventors: Ui Gab JOUNG, Dong Ok KIM, Dong Wook KIM, Ah Reum KIM, Hye Ran PARK, Kil SAGONG, Sung Hae JUN, Chun Sun LEE, Eun Yeong HWANG
  • Publication number: 20170222633
    Abstract: Provided is a semiconductor device including low power retention flip-flop. The semiconductor device includes a first line to which a global power supply voltage is applied, a second line to which a local power supply voltage is applied, the second line being separated from the first line, a first operating circuit connected to the second line to use the local power supply voltage, a first power gating circuit determining whether the local power supply voltage is applied to the first operating circuit and a first retention flip-flop connected to the first line and the second line, wherein the first retention flip-flop comprises a first circuit including a master latch, a second circuit including a slave latch, and a first tri-state inverter connected between the master latch and the slave latch.
    Type: Application
    Filed: January 5, 2017
    Publication date: August 3, 2017
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jong Woo KIM, Min Su KIM, Ah Reum KIM, Chung Hee KIM