Abstract: A separator for a fuel cell, which is stacked on a reaction layer including a membrane electrode assembly (MEA) and a gas diffusion layer (GDL) stacked on the MEA includes: a plate body stacked on the GDL; stepped portions, on which a reactant gas flows in a first direction, disposed on a first surface of the plate body, the first surface facing the GDL, the stepped portions disposed in a second direction that intersects the first direction in which the reactant gas flows; lands disposed on the stepped portions so as to be spaced apart from one another in the second direction, the lands being in contact with the GDL; first channels defined between the GDL and the stepped portions so as to be disposed between adjacent lands, the first channels configured such that the reactant gas flows along the first channels; and second channels defined between the plate body and the GDL so as to communicate with the first channels, the second channels configured such that the reactant gas flows along the second channels.

Abstract: Disclosed is a method of quantifying furan concentration to efficiently manage a deterioration state of a transformer in the field. The method of quantifying furan concentration includes: measuring a color-development degree of an extraction solution by making the extraction solution containing furan extracted from an insulating-oil sample mix and react with a color reagent; and quantifying furan concentration by correction based on a correlation between a precise analysis and a simple analysis with regard to the color-development degree of the extraction solution, wherein the precise analysis is to obtain a quantitative value through color column separation based on high performance liquid chromatography (HPLC) in a laboratory to analyze a furan compound in insulating oil of a transformer, and the simple analysis is to obtain a chromaticity value in a field with regard to actual transformer samples.

Abstract: A semiconductor device is provided. The semiconductor device includes a clock gate line supplying a clock signal, an inverted clock gate line disposed in parallel to the clock gate line and supplying an inverted clock signal, a first latch circuit performing a first latch operation based on the clock signal and the inverted clock signal and a second latch circuit disposed on a side of the first latch circuit in a first direction, receiving an output of the first latch circuit, and operating based on the clock signal and the inverted clock, wherein the clock gate line and the inverted clock gate line extend in the first direction and are shared by the first and second latch circuits.

Abstract: A semiconductor circuit and a layout system of the semiconductor circuit, the semiconductor circuit including a latch; a feedback inverter that receives an output signal of the latch via a first node and provides a feedback signal to the latch responsive to the output signal of the latch; and an output driver which receives the output signal of the latch via the first node and provides an output signal externally of the semiconductor circuit. The output driver includes an even number of inverters, and the latch, the feedback inverter, and the output driver share a single active region formed without isolation.

Abstract: Provided is a hybrid catalyst composition including a first transition metal compound represented by Formula 1 and a second transition metal compound represented by Formula 2, the compounds being different from each other in the Formulae. The hybrid catalyst composition including the first and second transition metal compounds may exhibit high catalytic activity and may prepare a polyolefin having processability and mechanical properties.

Abstract: A display device includes a display panel including a plurality of pixel rows, and a panel driver configured to drive the display panel. The panel driver includes a scan on time decider configured to receive line image data for each of the plurality of pixel rows, and to determine a scan on time change amount for each of the plurality of pixel rows based on the line image data, and a scan control block configured to adjust a scan pulse applied to each of the plurality of pixel rows according to the scan on time change amount.

Abstract: A semiconductor device is provided. The semiconductor device includes a clock gate line supplying a clock signal, an inverted clock gate line disposed in parallel to the clock gate line and supplying an inverted clock signal, a first latch circuit performing a first latch operation based on the clock signal and the inverted clock signal and a second latch circuit disposed on a side of the first latch circuit in a first direction, receiving an output of the first latch circuit, and operating based on the clock signal and the inverted clock, wherein the clock gate line and the inverted clock gate line extend in the first direction and are shared by the first and second latch circuits.

Abstract: An integrated circuit includes a semiconductor substrate, first through third power rails, first through third selection gate lines, and a row connection wiring. The first through third power rails on the semiconductor substrate extend in a first direction and arranged sequentially in a second direction perpendicular to the first direction. The first through third selection gate lines on the semiconductor substrate extend in the second direction over a first region between the first power rail and the second power rail and a second region between the second power rail and the third power rail, and are arranged sequentially in the first direction. The row connection wiring on the semiconductor substrate extends in the first direction to connect the first selection gate line and the third selection gate line.

Abstract: The invention relates to: a hybrid supported metallocene catalyst includes at least one first metallocene compound among the compounds represented by chemical formula 1, at least one second metallocene compound among the compounds represented by chemical formula 2 and a cocatalyst compound; a method for preparing an ethylene-?-olefin copolymer, comprising polymerizing olefin monomers in the presence thereof; and an ethylene-?-olefin copolymer having improved melt strength.

Abstract: A display device includes a display panel including a plurality of pixel rows, and a panel driver configured to drive the display panel. The panel driver includes a scan on time decider configured to receive line image data for each of the plurality of pixel rows, and to determine a scan on time change amount for each of the plurality of pixel rows based on the line image data, and a scan control block configured to adjust a scan pulse applied to each of the plurality of pixel rows according to the scan on time change amount.

Abstract: A semiconductor circuit and a layout system of the semiconductor circuit, the semiconductor circuit including a latch; a feedback inverter that receives an output signal of the latch via a first node and provides a feedback signal to the latch responsive to the output signal of the latch; and an output driver which receives the output signal of the latch via the first node and provides an output signal externally of the semiconductor circuit. The output driver includes an even number of inverters, and the latch, the feedback inverter, and the output driver share a single active region formed without isolation.

Abstract: A flip-flop generates a first feedback signal using a signal generated inside the flip-flop. The flip-flop includes a first stage circuit, a second stage circuit and a third stage circuit. The first stage circuit receives a first data signal and a clock signal and generates a first internal signal through a first node. The second stage circuit receives the first internal signal, the clock signal, and the first feedback signal and generates a second internal signal through a second node. The third stage circuit generates a second data signal by latching the second internal signal when the clock signal is at a first level, using the second internal signal and the clock signal. The second stage circuit cuts off at least one first current path between the second node and a power supply, based on the first feedback signal, when the clock signal is at a second level.

Abstract: Provided are semiconductor circuits. A semiconductor circuit includes: a first circuit configured to propagate a value of a first node to a second node based on a voltage level of a clock signal; a second circuit configured to propagate a value of the second node to a third node based on the voltage level of the clock signal; and a third circuit configured to determine a value of the third node based on a voltage level of the second node and the voltage level of the clock signal, wherein the first circuit comprises a first transistor gated to a voltage level of the first node, a second transistor connected in series with the first transistor and gated to the voltage level of the third node, and a third transistor connected in parallel with the first and second transistors and gated to a voltage level of the clock signal to provide the value of the first node to the second node.

Abstract: An integrated circuit includes a semiconductor substrate, first through third power rails, first through third selection gate lines, and a row connection wiring. The first through third power rails on the semiconductor substrate extend in a first direction and arranged sequentially in a second direction perpendicular to the first direction. The first through third selection gate lines on the semiconductor substrate extend in the second direction over a first region between the first power rail and the second power rail and a second region between the second power rail and the third power rail, and are arranged sequentially in the first direction. The row connection wiring on the semiconductor substrate extends in the first direction to connect the first selection gate line and the third selection gate line.

Abstract: Provided is a semiconductor device including low power retention flip-flop. The semiconductor device includes a first line to which a global power supply voltage is applied, a second line to which a local power supply voltage is applied, the second line being separated from the first line, a first operating circuit connected to the second line to use the local power supply voltage, a first power gating circuit determining whether the local power supply voltage is applied to the first operating circuit and a first retention flip-flop connected to the first line and the second line, wherein the first retention flip-flop comprises a first circuit including a master latch, a second circuit including a slave latch, and a first tri-state inverter connected between the master latch and the slave latch.

Abstract: Provided are semiconductor circuits. A semiconductor circuit includes: a first circuit configured to propagate a value of a first node to a second node based on a voltage level of a clock signal; a second circuit configured to propagate a value of the second node to a third node based on the voltage level of the clock signal; and a third circuit configured to determine a value of the third node based on a voltage level of the second node and the voltage level of the clock signal, wherein the first circuit comprises a first transistor gated to a voltage level of the first node, a second transistor connected in series with the first transistor and gated to the voltage level of the third node, and a third transistor connected in parallel with the first and second transistors and gated to a voltage level of the clock signal to provide the value of the first node to the second node.

Abstract: Provided is a hybrid catalyst composition including a first transition metal compound represented by Formula 1 and a second transition metal compound represented by Formula 2, the compounds being different from each other in the Formulae. The hybrid catalyst composition including the first and second transition metal compounds may exhibit high catalytic activity and may prepare a polyolefin having processability and mechanical properties.

Abstract: A method and an apparatus for distinguishing radionuclides are disclosed. The method comprises the steps of: receiving energy generated in one or more radioactive elements; applying energy as a weight for each channel to spectrum of the received energy; and distinguishing the one or more radioactive elements on the basis of the spectrum of the spectrum to which the weight is applied. A radioactive element having an energy value corresponding to a peak value of the spectrum of the energy to which the weight is applied, as an energy value of a Compton edge, is distinguished as the one or more radioactive elements. According to the present invention, it is possible to more accurately monitor radiation even while using a plastic scintillator, and further to improve energy resolution of a plastic scintillator.

Abstract: The present disclosure relates to a method for inducing pluripotent stem cells by inducing reprogramming and/or dedifferentiation of differentiated adult cells using shikimic acid, a plant extract or plant stem cells containing shikimic acid and an extract of dedifferentiated stem cells (callus), pluripotent stem cells prepared by the method and a composition containing the pluripotent stem cells. In accordance with the present disclosure, ethical concerns implicated with the use of eggs to prepare pluripotent stem cells such as embryonic stem cell can be resolved. And, because the plant stem cell extract unharmful to human is used, pluripotent stem cells with proven safety can be prepared and they may be used to develop immunocompatible cell therapy agents suited for individuals. In addition, by pluripotent stem cells from individuals having diseases, the present disclosure will be very useful in studying the cause of diseases and devolving therapeutic strategy.

Abstract: Provided are semiconductor circuits. A semiconductor circuit includes: a first circuit configured to propagate a value of a first node to a second node based on a voltage level of a clock signal; a second circuit configured to propagate a value of the second node to a third node based on the voltage level of the clock signal; and a third circuit configured to determine a value of the third node based on a voltage level of the second node and the voltage level of the clock signal, wherein the first circuit comprises a first transistor gated to a voltage level of the first node, a second transistor connected in series with the first transistor and gated to the voltage level of the third node, and a third transistor connected in parallel with the first and second transistors and gated to a voltage level of the clock signal to provide the value of the first node to the second node.