Abstract: A phase lock loop monitors the frequency of redundant input clock signals and switches back and forth therebetween should one or the other become invalid. Thus, the PLL may continue normal operation even with a failure of one input clock signal. If both the input clock signals fail, an internal reference signal maintains the PLL at a nominal operating frequency until one of the input clock signals is restored whereby the loop can quickly re-establish phase lock. To determined validity, the input clock signals are sampled and stored by the reference signal in a predetermined manner. The input clock signal is valid if the samples of the input clock signal each have the same logic state after the sampling period; otherwise, the input clock signal is invalid if the samples of the input clock signal have at least one different logic state after the sampling period.

Abstract: A voltage controlled oscillator (VCO) generates a 50% duty cycle clock. The 50% duty cycle clock is derived directly from the operating frequency of the VCO thereby abating the need for the VCO to operate at twice the desired clock frequency. This allows the VCO to be utilized in high frequency phase-locked loop systems.

Abstract: A voltage controlled oscillator (VCO) includes a voltage controlled load. The voltage controlled load supplies additional capacitive loading to the VCO, via a transmission gate, at low frequencies to decrease the frequency-gain factor of the VCO. Moreover, at high frequencies, the effect of the voltage controlled load is minimized by turning off the transmission gate thereby allowing the VCO to operate at maximum frequency for worst case speed conditions.

Abstract: A PLL lock indicator circuit for indicating when a phase-lock-loop circuit is in lock includes a gate circuit coupled to the phase/frequency detector of the phase-lock-loop circuit for providing an output logic signal that is responsive to output logic signals from the phase/frequency detector being in a predetermined state. A counter circuit is enabled by the output logic signal of the gate circuit for providing an output logic signal when the counter circuit has reached a predetermined count. A latch circuit is responsive to the output logic signal of the counter circuit for providing a lock signal at an output terminal of the circuit, the lock signal being indicative of when the PLL circuit is in phase lock.