Abstract: A crossbar switch device for a processor block ASIC core and a method for a flush-posted-write(s)-before-read mode thereof are described. Operation for the flush-posted-write(s)-before-read mode is set in a first processor block interface coupled to programmable logic fabric. At least one write command is sent from a transaction initiating device instantiated using the programmable logic fabric to the first processor block interface. The at least one write command is posted in the first processor block interface. At least one write command received is stored in a command queue of the crossbar switch device. A read command initiated by a microprocessor is sent to the crossbar switch device. The at least one write command has an address overlap with the read command with respect to a destination target. The read command is temporarily blocked in the crossbar switch device until a command phase of the at least one write command is completed.

Abstract: A system for implementing a non-volatile input/output (I/O) device based memory can include an interface configured to receive a processor request specifying a data unit. The data unit can be specified by a processor address. The system can include an address-data converter coupled to the interface. The address-data converter can be configured to correlate the processor address of the data unit to a data block within the non-volatile I/O device. The system further can include an I/O controller coupled to the address-data converter. The I/O controller can be configured to issue a non-volatile I/O device command specifying the data block to the non-volatile I/O device.

Abstract: A hardwired core is embedded in an integrated circuit having programmable circuitry. The hardwired core has a microprocessor; a crossbar interconnect coupled to processor local buses of the microprocessor; and a memory controller interface coupled to the crossbar interconnect. The crossbar interconnect provides pipelines for coupling the hardwired core to the programmable circuitry. The microprocessor, the crossbar interconnect, and the memory controller interface are all capable of operating at a first frequency of operation, and the memory controller interface is further capable of being set to operate at a second frequency of operation having an integer ratio with respect to the first frequency of operation. The crossbar interconnect is configured to direct transactions initiated by the microprocessor to the memory controller interface for accessing one or more memory devices coupled to the memory controller interface via a memory controller.

Abstract: A method for address acknowledgement is described. A memory controller interface is embedded as part of an embedded core in a host integrated circuit. Access to the memory controller interface is arbitrated with an arbiter. An accept signal is sent from the memory controller interface to the arbiter to indicate whether the memory controller interface is ready to receive a transaction. Access to the memory controller interface is requested by a master device for passing the transaction to a memory controller via the arbiter. The arbiter is a proxy for the memory controller interface responsive to the accept signal being asserted. An acknowledgement signal is sent from the arbiter as a proxy for the memory controller interface responsive to receipt of the transaction and the accept signal being asserted.

Abstract: A processor local bus bridge for a processor block ASIC core for embedding in an IC is described. A core logic-to-core logic bridge includes a slave processor local bus interface, a crossbar switch coupled to the slave processor local bus interface and a master processor local bus interface coupled to the crossbar switch. The slave processor local bus interface and the master processor local bus interface are coupled to one another via the crossbar switch for bidirectional communication between a first and a second portion of core logic. The bridge provides rate adaptation for bridging for use of a frequency of operation associated with the crossbar switch which has substantially greater frequencies of operation than those associated with the core logic sides of the master and slave processor local bus interfaces.

Abstract: A method of bridging a plurality of buses within a bus bridge can include determining whether a queue of the bus bridge includes a transaction request directed to a restricted address range and, for each received transaction request, determining whether an address to which the transaction request is directed is within the restricted address range. Each transaction request received by the bus bridge can be selectively rejected according to whether the address to which the transaction request is directed is within the restricted address range and whether the queue includes a transaction request directed to the restricted address range.

Abstract: An embodiment of a method of enhancing security of internal memory is disclosed. For this embodiment of the method, the application specific block is operated in a functional mode, and a reset of the application specific block is initiated. From a built-in self-test engine, at least one write to the internal memory is initiated in response to the reset initiated, where the at least one write overwrites data stored in the internal memory during a reset mode.

Abstract: A method for decoding, including: obtaining an op-code from a master device; setting a mode to mask a first portion of the bits of the op-code, where the first portion of the bits are for being treated as a wildcard value; and decoding a second portion of the op-code that is not masked to determine whether the op-code is for a slave device. The decoding of the second portion is performed by a controller having a decoder, and the controller bridges the master device for communication with the slave device. The decoding of the first portion of the bits is performed by the slave device. The first portion of the bits identifies an instruction from a group of instructions, and the group of instructions uses a single configuration register of registers of the controller.

Abstract: A method and controller for supporting out of order execution of instructions is described. A microprocessor is coupled to a coprocessor via a controller. Instructions are received by the microprocessor and the controller. Indices respectively associated with the instructions are generated by the microprocessor, and the instructions are popped from the first queue for execution by the coprocessor. The controller includes a first queue and a second queue. The instructions and the indices are queued in the first queue, and this first queuing includes steering the instructions and the indices associated therewith to respective first register locations while maintaining association between the instructions and the indices. The instructions may be popped off the first queue out of order with respect to an order in which the instructions are received into the first queue.

Abstract: A device control register controller for a processor block Application Specific Integrated Circuit (“ASIC”) core is described. Device control register slave blocks are coupled to the device control register controller and have access to device registers for a plurality of interfaces of the processor block ASIC core. A master device interface is for coupling at least one slave device external to the processor block ASIC core to the device control register controller. A slave device interface is for coupling a master device external to the processor block ASIC core to the device control register controller.

Abstract: Command translation of burst commands is described. A slave processor local bus (“PLB”) bridge, part of a processor block core embedded in a host IC, has a data size threshold to allow access to a crossbar switch device. A master device, coupled to the slave PLB bridge, has any of a plurality of command bus widths. A burst command is issued via a command bus, having a command bus width of the plurality, from the master device for the slave PLB bridge. The burst command is converted to a native bus width of the slave processor logic block if the command bus width is not equal to the native bus width. The burst command is translated if execution of the burst command will exceed the data size threshold and passed without the translating if the execution of the burst command will not exceed the data size threshold.

Abstract: An ASIC block embedded in a host IC has a first clock domain with a first frequency of operation that is at least equal to a second frequency of operation of a second clock domain in the host IC but external to the ASIC block. FPGA logic in the second clock domain interfaces with the ASIC block; and a PLL located in the host integrated circuit but external to the ASIC block is coupled to receive a reference clock signal and configured to generate clock signals. Two of the clock signals are respectively sent to the FPGA logic and the ASIC block to make one appear to be produced earlier in time than the other with respect to the ASIC block to compensate for a clock insertion delay and for a clock-to-output time associated with the FPGA logic that at least approximates zero.

Abstract: Arbitration for a processor block core is described. Master devices are associated with a processor block core embedded in a host integrated circuit (“IC”). The master devices are coupled to core logic of the host IC via a crossbar switch and a bridge, which are part of the processor block core. The crossbar switch includes an arbiter. An arbitration protocol is selected from among a plurality of arbitration protocols for use by the arbiter. Pending transactions having are polled for access to the bridge for arbitration using the arbitration protocol selected.

Abstract: A method of enabling variable latency data transfers in an electronic device, such as an FPGA with an embedded processor, is described. According to one aspect of the invention, a method comprises steps of providing an address for a data transfer between a memory controller and a peripheral device; coupling an address valid signal to the peripheral device; transferring the data between the memory controller and the peripheral device; and receiving a data transfer complete signal at the memory controller. According to another aspect of the invention, an integrated circuit enabling a variable latency data transfer is described. The integrated circuit comprises peripheral device; a memory controller coupled to the peripheral device; an address valid signal coupled from the memory controller to the peripheral device; and a transfer complete signal coupled from the peripheral device to the memory controller.

Abstract: A vector transfer unit for handling transfers of vector data between a memory and a data processor in a computer system. Vector data transfer instructions are posted to an instruction queue in the vector transfer unit. Program instructions for performing a burst transfer include determining the starting address of the vector data to be transferred, the ending address of the vector data to be transferred, and whether the ending address of the vector data to be transferred is within the same virtual memory page as the starting address. The ending address of the vector data to be transferred is determined based on the number of data elements to be transferred, the stride of the vector data to be transferred, and the width of the vector data elements to be transferred. When the amount of data to be transferred is divisible by a factor of two, the multiplication of the stride and width of the data elements is carried out by shifting.

Abstract: Method and apparatus for indicating to a coprocessor when the coprocessor can update internal register content thereof without negative repercussion to a processor is described. A controller is coupled between the coprocessor and a processor, where the controller is configured with a state machine to track the instruction through pipeline stages of the processor.

Abstract: Method of informing a processor that a coprocessor instruction is not executable by a coprocessor is described. The coprocessor, instantiated in configurable logic, is configured to execute a subset of coprocessor instructions, excluding user-selected instructions not instantiated. The processor is coupled to the coprocessor via a controller. The coprocessor instruction is sent from the processor to the controller, which queries control logic to determine whether the coprocessor is configured to execute the coprocessor instruction. If a control bit is set to disable an instruction or group of instructions, the coprocessor instruction is not executable by the coprocessor.

Abstract: A controller interface between a processor and a coprocessor is described. The controller is coupled to the processor to provide a processor interface for operating at a first frequency, where the first frequency is a frequency of operation of the processor. The controller is coupled to the coprocessor to provide a coprocessor interface for operating at a second frequency, where the second frequency is a frequency of operation of the coprocessor which is slower than or equal to the first frequency. The controller is configured to operate at both the first frequency and the second frequency providing in part handshaking between the processor and the coprocessor such that the processor does not have to be slowed down to the second frequency for operation with the coprocessor.

Abstract: A system is disclosed comprising a logic circuit in an integrated circuit device, wherein the logic circuit comprises a logic fabric that includes a plurality of configurable logic blocks, switching blocks, and input/output blocks, wherein the logic fabric is configured according to configuration data provided to the integrated circuit device from an external memory and at least a portion of the logic fabric is configured as a configured processor to perform a first fixed logic function according to the configuration data. A fixed logic processor, a first auxiliary processing interface, a second fixed logic processor, a second auxiliary processing interface enable communication with the configured processor, wherein the configured processor remains configured to enable both the fixed logic processor and the second fixed logic processor to access the configured processor to perform the fixed logic function.

Abstract: Method and apparatus for generating a test program for an integrated circuit having an embedded processor. One embodiment has a system which includes an embedded microprocessor; a plurality of assembly language instructions stored in a memory, where the assembly language instructions substantially exercise a critical path or a path closest to the critical path in the embedded microprocessor; and programmable test circuitry having a programmable clock circuit for providing a multiplied clock signal to the embedded microprocessor in order to execute the assembly language instructions.