Abstract: The present disclosure is directed to dynamically prioritizing, selecting or ordering a plurality threads for execution by processor circuitry based on a quality of service and/or class of service value/indicia assigned to the thread by an operating system executed by the processor circuitry. As threads are executed by processor circuitry, the operating system dynamically updates/associates respective class of service data with each of the plurality of threads. The current quality of service/class of service data assigned to the thread by the operating system is stored in a manufacturer specific register (MSR) associated with the respective thread. Selection circuitry polls the MSRs on a periodic, aperiodic, intermittent, continuous, or event-driven basis and determines an execution sequence based on the current class of service value associated with each of the plurality of threads.

Abstract: Embodiments of the present disclosure describe methods, apparatuses, storage media, and systems for routing data packets in a quality of service (QoS) enabled content-based network or interconnect fabric. Various embodiments describe how to manage data flow based on content-based attribute vectors (AVs) indicating QoS requirements with respect to the data packets in networking or platform interconnects. A dynamic scheduling based on AV information may improve trafficking efficiency and optimize system performance.

Abstract: The present disclosure is directed to dynamically prioritizing, selecting or ordering a plurality threads for execution by processor circuitry based on a quality of service and/or class of service value/indicia assigned to the thread by an operating system executed by the processor circuitry. As threads are executed by processor circuitry, the operating system dynamically updates/associates respective class of service data with each of the plurality of threads. The current quality of service/class of service data assigned to the thread by the operating system is stored in a manufacturer specific register (MSR) associated with the respective thread. Selection circuitry polls the MSRs on a periodic, aperiodic, intermittent, continuous, or event-driven basis and determines an execution sequence based on the current class of service value associated with each of the plurality of threads.

Abstract: Embodiments of the present disclosure describe methods, apparatuses, storage media, and systems for routing data packets in a quality of service (QoS) enabled content-based network or interconnect fabric. Various embodiments describe how to manage data flow based on content-based attribute vectors (AVs) indicating QoS requirements with respect to the data packets in networking or platform interconnects. A dynamic scheduling based on AV information may improve trafficking efficiency and optimize system performance.

Abstract: A method is provided for each router to individually manage retransmissions at run time in a single chip computer die or a single computer that includes cores or compute nodes and routers that interconnect the cores or the compute nodes. Each router compares static energy saving and dynamic energy increase from turning off a retransmission buffer of the router in a monitoring phase. When the static energy saving is greater than the dynamic energy increase, the router turns off the retransmission buffer in a subsequent monitoring phase. When the static energy saving is less than the dynamic energy increase, the router turns on the retransmission buffer in the subsequent monitoring phase.

Abstract: A method of an aspect includes running a plurality of threads on a plurality of thread processors. Memory accesses, of a thread of the plurality that is running on a first thread processor of the plurality, are monitored to both a first memory through a first memory controller and a second memory through a second memory controller. A second thread processor of the plurality is selected for a thread based on the monitoring of the memory accesses of the thread to both the first memory and the second memory. Installation of the thread, for which the second thread processor was selected, is initiated on the second thread processor. Other methods, apparatus, and systems are also disclosed.

Abstract: A method and apparatus for selectively parking routers used for routing traffic in mesh interconnects. Various router parking (RP) algorithms are disclosed, including an aggressive RP algorithm where a minimum number of routers are kept active to ensure adequate network connectivity between active nodes and/or intercommunicating nodes, leading to a maximum reduction in static power consumption, and a conservative RP algorithm that favors network latency considerations over static power consumption while also reducing power. An adaptive RP algorithm is also disclosed that implements aspects of the aggressive and conservative RP algorithms to balance power consumption and latency considerations in response to ongoing node utilization and associated traffic. The techniques may be implemented in internal network structures, such as for single chip computers, as well as external network structures, such as computing clusters and massively parallel computer architectures.

Abstract: A method of an aspect includes running a plurality of threads on a plurality of thread processors. Memory accesses, of a thread of the plurality that is running on a first thread processor of the plurality, are monitored to both a first memory through a first memory controller and a second memory through a second memory controller. A second thread processor of the plurality is selected for a thread based on the monitoring of the memory accesses of the thread to both the first memory and the second memory. Installation of the thread, for which the second thread processor was selected, is initiated on the second thread processor. Other methods, apparatus, and systems are also disclosed.

Abstract: Methods, apparatus and systems for improved performance and energy efficiency of software-based routers. A software router running on a host computer system employing multiple Network Interface Controllers (NICs) maintains a routing table wherein packet flows are classified as managed flows (MFs) under which packets are received at and forwarded from the same NIC and unmanaged flows UFs under which packets are received at and forwarded from different NICs. Forwarding table data is employed by a NIC to facilitate packet identification and flow classification operations under which the NIC determines whether a received packet is an MF, UF, or an unclassified flow. Under various schemes, packet forwarding for MFs is handled by the software router architecture such that either only the packet header is copied into memory in the host or the entire packet forwarding is handled by the NIC.

Abstract: An apparatus and method for efficient handling of critical chunks. For example, one embodiment of an apparatus comprises a plurality of agents to perform a respective plurality of data processing functions, at least one of the data processing functions comprising transmitting and receiving chunks of data to and from a memory controller, respectively; a system agent to coordinate requests for transmitting and receiving the chunks of data to and from the memory controller, the system agent comprising: a memory for temporarily storing the chunks of data during transmission between the agents and the memory controller; and scheduling logic to prioritize critical chunks over non-critical chunks across multiple outstanding requests while ensuring that the non-critical chunks do not result in starvation.

Abstract: The present disclosure provides techniques for cache management. A data block may be received from an IO interface. After receiving the data block, the occupancy level of a cache memory may be determined. The data block may be directed to a main memory if the occupancy level exceeds a threshold. The data block may be directed to a cache memory if the occupancy level is below a threshold.

Abstract: Memory eviction that recognizes not all evictions have an equal cost on system performance. A management device keeps a weight and/or a count associated with each portion of memory. Each memory portion is associated with a source agent that generates requests to the memory portion. The management device adjusts the weight by a cost factor indicating a latency impact that could occur if the evicted memory portion is again requested after being evicted. The latency impact is a latency impact for the associated source agent to replace the memory portion. In response to detecting an eviction trigger for the memory device, the management device can identify a memory portion having a most extreme weight, such as a highest or lowest value weight. The management device replaces the identified memory portion with a memory portion that triggered the eviction.

Abstract: Methods and apparatus for implementing active interconnect link power management using an adaptive low-power link-state entry policy. The power state of an interconnect link or fabric is changed in response to applicable conditions determined by low-power link-state entry policy logic in view of runtime traffic on the interconnect link or fabric. The low-power link-state policy logic may be configured to include consideration of operating system input and Quality of Service (QoS) requirements for applications and devices employing the link or fabric, and device latency tolerance requirements.

Abstract: In one embodiment, the present invention includes a method for obtaining file information regarding a file to be downloaded from a remote location to a computing device, creating at least one empty file in a destination storage based on the file information and communicating block information regarding the empty file to a network interface, and receiving a data packet of the file in the network interface and directly sending a payload of the data packet from the network interface to the destination storage according to the block information, while a host processor of the computing device is in a low power state. Other embodiments are described and claimed.

Abstract: A method is provided for each router to individually manage retransmissions at run time in a single chip computer die or a single computer that includes cores or compute nodes and routers that interconnect the cores or the compute nodes. Each router compares static energy saving and dynamic energy increase from turning off a retransmission buffer of the router in a monitoring phase. When the static energy saving is greater than the dynamic energy increase, the router turns off the retransmission buffer in a subsequent monitoring phase. When the static energy saving is less than the dynamic energy increase, the router turns on the retransmission buffer in the subsequent monitoring phase.

Abstract: In an embodiment, a processor includes multiple tiles, each including a core and a tile cache hierarchy. This tile cache hierarchy includes a first level cache, a mid-level cache (MLC) and a last level cache (LLC), and each of these caches is private to the tile. A controller coupled to the tiles includes a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a tile and to cause the LLC of the tile to be independently power gated, based at least in part on this information. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes multiple tiles, each including a core and a tile cache hierarchy. This tile cache hierarchy includes a first level cache, a mid-level cache (MLC) and a last level cache (LLC), and each of these caches is private to the tile. A controller coupled to the tiles includes a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a tile and to cause the LLC of the tile to be independently power gated, based at least in part on this information. Other embodiments are described and claimed.

Abstract: An apparatus and method for efficient handling of critical chunks. For example, one embodiment of an apparatus comprises a plurality of agents to perform a respective plurality of data processing functions, at least one of the data processing functions comprising transmitting and receiving chunks of data to and from a memory controller, respectively; a system agent to coordinate requests for transmitting and receiving the chunks of data to and from the memory controller, the system agent comprising: a memory for temporarily storing the chunks of data during transmission between the agents and the memory controller; and scheduling logic to prioritize critical chunks over non-critical chunks across multiple outstanding requests while ensuring that the non-critical chunks do not result in starvation.

Abstract: The present invention may provide a computer system including a plurality of tiles divided into multiple virtual domains. Each tile may include a router to communicate with others of said tiles, a private cache to store data, and a spill table to record pointers for data evicted from the private cache to a remote host, wherein the remote host and the respective tile are provided in the same virtual domain. The spill tables may allow for faster retrieval of previously evicted data because the home registry does not need to be referenced if requested data is listed in the spill table. Therefore, embodiments of the present invention may provide a distance-aware cache collaboration architecture without incurring extraneous overhead expenses.

Abstract: Methods and apparatus for implementing active interconnect link power management using an adaptive low-power link-state entry policy. The power state of an interconnect link or fabric is changed in response to applicable conditions determined by low-power link-state entry policy logic in view of runtime traffic on the interconnect link or fabric. The low-power link-state policy logic may be configured to include consideration of operating system input and Quality of Service (QoS) requirements for applications and devices employing the link or fabric, and device latency tolerance requirements.