Patents by Inventor Ai-Sen Liu

Ai-Sen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10504594
    Abstract: A non-volatile memory includes a back gate, a first graphene ribbon layer, a dielectric layer, a second graphene ribbon layer and a porous dielectric layer. The back gate is disposed in a substrate. The first graphene ribbon layer is disposed on the substrate. The dielectric layer covers the first graphene ribbon layer but exposes an exposed part of the first graphene ribbon layer. The second graphene ribbon layer including two end parts connected by a cantilever part is disposed above the first graphene ribbon layer, and the cantilever part is right above the exposed part of the first graphene ribbon layer. The porous dielectric layer is disposed on the dielectric layer and seals the cantilever part. The present invention also provides a method of forming said non-volatile memory.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: December 10, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ai-Sen Liu, Bin-Siang Tsai, Chin-Fu Lin
  • Publication number: 20190229053
    Abstract: A manufacturing method of a metal-insulator-metal (MIM) capacitor structure includes the following steps. A bottom plate is formed. A first conductive layer is patterned to be the bottom plate, and the first conductive layer includes a metal element. An interface layer is formed on the first conductive layer by performing a nitrous oxide (N2O) treatment on a top surface of the first conductive layer. The interface layer includes oxygen and the metal element of the first conductive layer. A dielectric layer is formed on the interface layer. A top plate is formed on the dielectric layer. The metal-insulator-metal capacitor structure includes the bottom plate, the interface layer disposed on the bottom plate, the dielectric layer disposed on the interface layer, and the top plate disposed on the dielectric layer.
    Type: Application
    Filed: January 22, 2018
    Publication date: July 25, 2019
    Inventors: Ya-Jyuan Hung, Ai-Sen Liu, Bin-Siang Tsai, Chin-Fu Lin, Chun-Yuan Wu
  • Patent number: 9966425
    Abstract: A method for fabricating a metal-insulator-metal (MIM) capacitor includes the steps of: forming a capacitor bottom metal (CBM) layer on a material layer; forming a silicon layer on the CBM layer; forming a capacitor dielectric layer on the silicon layer; and forming a capacitor top metal (CTM) layer on the capacitor dielectric layer.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: May 8, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Jen-Po Huang, Chin-Fu Lin, Bin-Siang Tsai, Xu Yang Shen, Seng Wah Liau, Yen-Chen Chen, Ko-Wei Lin, Chun-Ling Lin, Kuo-Chih Lai, Ai-Sen Liu, Chun-Yuan Wu, Yang-Ju Lu
  • Patent number: 9926488
    Abstract: A phosphor, having a general formula of K2[Si1-xGex]yF6:Mn1-y4+. The phosphor is excited to emit a light having a first main emission peak with a first maximum emission intensity and a first dominant wavelength, wherein a relative emission intensity S of the light of the phosphor is constantly greater than 85% across an temperature of the phosphor between 300 K and 470 K during operation, wherein S=(IT/IRT)*100%, IRT and IT are the first maximum emission intensity when the temperature of the phosphor is at 300 K and T during operation respectively, and 300 K<T?470K.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: March 27, 2018
    Assignee: EPISTAR CORPORATION
    Inventors: Chun Che Lin, Ling-Ling Wei, Ru-Shi Liu, Ming-Chi Hsu, Ai-Sen Liu
  • Publication number: 20170088773
    Abstract: An embodiment of the present disclosure discloses a phosphor material and a manufacturing method thereof. The general composition of the phosphor material is A2-xMO4:Eux, wherein A includes a single element or at least two elements selected from the group consisting of Ca, Sr, and Ba, M is Si, Ge or combination thereof, wherein x is greater than 0.01 and 2-x>0. The phosphor material can be excited by a first excitation wavelength and emit a first emission spectrum and, excited by a second excitation wavelength and emit a second emission spectrum. The first excitation wavelength is different from the second excitation wavelength, and the first emission spectrum is different from the second emission spectrum.
    Type: Application
    Filed: September 22, 2016
    Publication date: March 30, 2017
    Inventors: Shin-Ying Lin, Chun-Che Lin, Ru-Shi Liu, Ming-Chi Hsu, Ai-Sen Liu
  • Patent number: 9583680
    Abstract: An optical electrical device comprises a base and a transparent conductive structure on the base is disclosed. The base further comprises a light-emitting device and the transparent conductive structure comprises a transparent conductive oxide layer and a passivation layer on the transparent conductive oxide layer. The material of the transparent conductive oxide layer comprises transparent conductive metal oxide, such as ZnO. Furthermore, the transparent conductive metal oxide also comprises impurities, such as a carrier e.g. gallium.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: February 28, 2017
    Assignee: EPISTAR CORPORATION
    Inventors: Yung-Fu Chang, Meng-Chyi Wu, Chong-Long Ho, Ai-Sen Liu
  • Publication number: 20170044431
    Abstract: A phosphor, having a general formula of K2[Si1-xGex]yF6:Mn1-y4+. The phosphor is excited to emit a light having a first main emission peak with a first maximum emission intensity and a first dominant wavelength, wherein a relative emission intensity S of the light of the phosphor is constantly greater than 85% across an temperature of the phosphor between 300 K and 470 K during operation, wherein S=(IT/IRT)*100%, IRT and IT are the first maximum emission intensity when the temperature of the phosphor is at 300 K and T during operation respectively, and 300 K<T?470K.
    Type: Application
    Filed: August 14, 2015
    Publication date: February 16, 2017
    Inventors: Chun Che Lin, Ling-Ling Wei, Ru-Shi Liu, Ming-Chi Hsu, Ai-Sen Liu
  • Publication number: 20170002463
    Abstract: A thin-film deposition apparatus comprises a chamber; a carrier in the chamber; a showerhead on the carrier, wherein the showerhead comprises multiple first gas-dispensing holes, multiple second gas-dispensing holes and multiple plasma-generating portions; and a first gas inlet system for providing a first process gas, wherein the first process gas outputted from the multiple first gas-dispensing holes.
    Type: Application
    Filed: June 30, 2016
    Publication date: January 5, 2017
    Inventors: Nai-Wen Fan, Shau-Yi Chen, Ai-Sen Liu, Zhi Zhong Ke, Chien-Bao Lin, Wen-Hao Zhuo, Feng-Zhi Chen, Chien-Cheng Kuo, Shih-Hao Chan, Chih-Hao Chen, Wei-Chih Peng, Chia-Liang Hsu
  • Patent number: 9520281
    Abstract: A method of fabricating an epitaxial device, comprising: providing a substrate having a first surface and a normal direction; epitaxially forming a first transition layer in a first temperature on the first surface of the substrate and in-situ incorporating a porogen into the first transition layer; and adjusting the first temperature to a second temperature to burn out the porogen from the first transition layer to form a hollow component inside the first transition layer.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: December 13, 2016
    Assignee: EPISTAR CORPORATION
    Inventor: Ai-Sen Liu
  • Publication number: 20160064616
    Abstract: An optical electrical device comprises a base and a transparent conductive structure on the base is disclosed. The base further comprises a light-emitting device and the transparent conductive structure comprises a transparent conductive oxide layer and a passivation layer on the transparent conductive oxide layer. The material of the transparent conductive oxide layer comprises transparent conductive metal oxide, such as ZnO. Furthermore, the transparent conductive metal oxide also comprises impurities, such as a carrier e.g. gallium.
    Type: Application
    Filed: November 12, 2015
    Publication date: March 3, 2016
    Inventors: Yung-Fu CHANG, Meng-Chyi WU, Chong-Long HO, Ai-Sen LIU
  • Publication number: 20140264390
    Abstract: A method of fabricating an epitaxial device, comprising: providing a substrate having a first surface and a normal direction; epitaxially forming a first transition layer in a first temperature on the first surface of the substrate and in-situ incorporating a porogen into the first transition layer; and adjusting the first temperature to a second temperature to burn out the porogen from the first transition layer to form a hollow component inside the first transition layer.
    Type: Application
    Filed: March 11, 2014
    Publication date: September 18, 2014
    Applicant: Epistar Corporation
    Inventor: Ai-Sen LIU
  • Publication number: 20140203322
    Abstract: An optical electrical device comprises a base and a transparent conductive structure on the base is disclosed. The base further comprises a light-emitting device and the transparent conductive structure comprises a transparent conductive oxide layer and a passivation layer on the transparent conductive oxide layer. The material of the transparent conductive oxide layer comprises transparent conductive metal oxide, such as ZnO. Furthermore, the transparent conductive metal oxide also comprises impurities, such as a carrier e.g. gallium.
    Type: Application
    Filed: August 20, 2013
    Publication date: July 24, 2014
    Applicant: EPISTAR CORPORATION
    Inventors: Yung-Fu Chang, Meng-Chyi Wu, Chong-Long Ho, Ai-Sen Liu
  • Patent number: 8053894
    Abstract: Apparatus for forming a semiconductor structure comprising a first layer on top of a substrate wherein the first layer defines conductive regions such as copper interconnect lines and non-conductive regions such as dielectric materials. The conductive regions are covered by a second layer of a material different than the first layer such as for example nickel and then the structure is heat treated such that the interconnect lines and second metal, such as a copper interconnect line and a nickel second layer, interact with each other to form an alloy layer. The alloy layer has superior qualities for adhering to both the copper interconnect lines and a subsequently deposited dielectric material.
    Type: Grant
    Filed: August 26, 2005
    Date of Patent: November 8, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Kai Wan, Yih-Hsiung Lin, Ming-Ta Lei, Baw-Ching Perng, Cheng-Chung Lin, Chia-Hui Lin, Ai-Sen Liu
  • Patent number: 7633588
    Abstract: An LCD panel including a first substrate, a second substrate and a smectic liquid crystal layer is disclosed. The first substrate includes a first electrode, a second electrode and a first horizontal alignment film. The first electrode has plural first portions. The second electrode has plural second portions. The first portions are spaced by the second portions. The electrical field directions formed between the first portions and the second portions are perpendicular to the surface of the first substrate. The electrical field direction on each first portion is opposite to that on each second portion. The first horizontal alignment film covers the first and the second electrodes. The second substrate includes a second horizontal alignment film. The horizontal rubbing direction of the first horizontal alignment film is parallel to that of the second horizontal alignment film. The smectic liquid crystal layer is sealed between the first and the second substrates.
    Type: Grant
    Filed: August 25, 2005
    Date of Patent: December 15, 2009
    Assignee: Au Optronics Corp.
    Inventors: Tzu-Yuan Lin, Ren-Hung Huang, Po-Chang Wu, Shwu-Yun Tsay, Shune-Long Wu, Chia-Hsing Sun, Jin-Jei Wu, Po-Lun Chen, Ai-Sen Liu
  • Patent number: 7338909
    Abstract: A method and apparatus for locally etching a substrate area the method including providing a substrate comprising a process surface; depositing a material layer over the process surface; and, applying a wet etchant to cover a targeted etching portion of the process surface while excluding an adjacent surrounding area to selectively etch the material layer overlying the targeted etching portion.
    Type: Grant
    Filed: June 18, 2004
    Date of Patent: March 4, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Yu-Liang Lin, Henry Lo, Chung-Long Chang, Gorge Huang, Tony Lu, Gnesh Yeh, Candy Liang, Chun-Hsien Lin, Mei Sheng Zhou, Sunny Su, Ai-Sen Liu, Cheng-Lin Huang, Li-Jui Chen, Shih Che Wang
  • Patent number: 7271103
    Abstract: A Cu damascene structure is formed where Cu diffusion barrier is formed by treating the top surface of the surrounding low-k interlayer dielectric with nitrogen or carbon containing medium to form a silicon nitride or silicon carbide diffusion barrier rather than capping the top surface of the Cu with metal diffusion barrier as is conventionally done.
    Type: Grant
    Filed: October 17, 2003
    Date of Patent: September 18, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuei-Wu Huang, Ai-Sen Liu, Baw-Ching Perng, Ming-Ta Lei, Wen-Kai Wan, Cheng-Chung Lin, Yih-Shung Lin, Chia-Hui Lin
  • Patent number: 7176137
    Abstract: A method of forming pluralities of gate sidewall spacers each plurality comprising different associated gate sidewall spacer widths including providing a first plurality of gate structures; blanket depositing a first dielectric layer over the first plurality of gate structures; blanket depositing a second dielectric layer over the first dielectric layer; etching back through a thickness of the first and second dielectric layers; blanket depositing a first photoresist layer to cover the first plurality and patterning to selectively expose at least a second plurality of gate structures; isotropically etching the at least a second plurality of gate structures for a predetermined time period to selectively etch away a predetermined portion of the first dielectric layer; and, selectively etching away the second dielectric layer to leave gate structures comprising a plurality of associated sidewall spacer widths.
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: February 13, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Baw-Ching Perng, Yih-Shung Lin, Ming-Ta Lei, Ai-Sen Liu, Chia-Hui Lin, Cheng-Chung Lin
  • Publication number: 20060244887
    Abstract: An LCD panel including a first substrate, a second substrate and a smectic liquid crystal layer is disclosed. The first substrate includes a first electrode, a second electrode and a first horizontal alignment film. The first electrode has plural first portions. The second electrode has plural second portions. The first portions are spaced by the second portions. The electrical field directions formed between the first portions and the second portions are perpendicular to the surface of the first substrate. The electrical field direction on each first portion is opposite to that on each second portion. The first horizontal alignment film covers the first and the second electrodes. The second substrate includes a second horizontal alignment film. The horizontal rubbing direction of the first horizontal alignment film is parallel to that of the second horizontal alignment film. The smectic liquid crystal layer is sealed between the first and the second substrates.
    Type: Application
    Filed: August 25, 2005
    Publication date: November 2, 2006
    Inventors: Tzu-Yuan Lin, Ren-Hung Huang, Po-Chang Wu, Shwu-Yun Tsay, Shune-Long Wu, Chia-Hsing Sun, Jin-Jei Wu, Po-Lun Chen, Ai-Sen Liu
  • Patent number: 7083495
    Abstract: A wafer based APC method for controlling an oxide (Cu, or TaN) polish step is described and combines a feed forward model that compensates for incoming wafer variations with a feed backward model which compensates for CMP variations. The method is geared toward minimizing Rs 3? variations. A Rs target value is inputted with metrology data from previous processes that affects the width and thickness of the copper layer. A copper thickness target and polish time for the first wafer is determined. Post CMP measurement data of the first wafer is used to modify the polish rate with a disturbance factor and an updated polish time is computed for subsequent wafers. The CMP recipe for each wafer is adjusted with metrology data and post CMP measurements. The APC method is successful in controlling copper Rs variations for the 90 nm technology node and is independent of copper pattern density.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: August 1, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsien Lin, Ai-Sen Liu, Sunny Wu, Yu-Liang Lin, Henry Lo, Mei-Sheng Zhou
  • Publication number: 20060113616
    Abstract: A method of forming spacers with different widths on a semiconductor substrate, includes the steps of disposing a first spacer layer over the substrate, defining the first spacer layer into a plurality of spacers of a first width, and disposing a second spacer layer selectively over the first spacer layer of a number of the spacers preselected for the second spacer layer, the predetermined number of the spacers with the second spacer layer each having a second width which is different from the first width.
    Type: Application
    Filed: August 18, 2005
    Publication date: June 1, 2006
    Inventors: Ai-Sen Liu, Baw-Ching Perng, Ming-Ta Lei, Yih-Shung Lin, Cheng-Chung Lin, Chia-Hui Lin